Index: firmware/include/adc.h
===================================================================
diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823
--- firmware/include/adc.h	(.../adc.h)	(revision 792764062d7b7826af10e030277f18379af4fcd1)
+++ firmware/include/adc.h	(.../adc.h)	(revision abb9687e52d9db5df1abe7626ba04a6d431ba823)
@@ -230,53 +230,30 @@
 }adc_config_reg_t;
 
 #define ADC1_OPMODECR_CONFIGVALUE		0x81140001U
-#define ADC1_CLOCKCR_CONFIGVALUE		(10U)
+#define ADC1_CLOCKCR_CONFIGVALUE		(25U)
 
 #define ADC1_G0MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U)
-#define ADC1_G1MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G1MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000020U | (uint32)0x00000000U | (uint32)0x00000000U)
 #define ADC1_G2MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
 
 #define ADC1_G0SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
 #define ADC1_G1SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
 #define ADC1_G2SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
 
-#define ADC1_BNDCR_CONFIGVALUE			((uint32)((uint32)8U << 16U)|(8U + 8U))
+#define ADC1_BNDCR_CONFIGVALUE			((uint32)((uint32)0U << 16U)|(0U + 10U))
 #define ADC1_BNDEND_CONFIGVALUE			(2U)
 
-#define ADC1_G0SAMP_CONFIGVALUE			(1U)
-#define ADC1_G1SAMP_CONFIGVALUE			(1U)
-#define ADC1_G2SAMP_CONFIGVALUE			(1U)
+#define ADC1_G0SAMP_CONFIGVALUE			(0U)
+#define ADC1_G1SAMP_CONFIGVALUE			(0U)
+#define ADC1_G2SAMP_CONFIGVALUE			(0U)
 
 #define ADC1_G0SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
 #define ADC1_G1SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
 #define ADC1_G2SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
 
 #define ADC1_PARCR_CONFIGVALUE			(0x00000005U)
 
-#define ADC2_OPMODECR_CONFIGVALUE		0x81140001U
-#define ADC2_CLOCKCR_CONFIGVALUE		(10U)
 
-#define ADC2_G0MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U)
-#define ADC2_G1MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
-#define ADC2_G2MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
-
-#define ADC2_G0SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC2_EVENT)
-#define ADC2_G1SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC2_EVENT)
-#define ADC2_G2SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC2_EVENT)
-
-#define ADC2_BNDCR_CONFIGVALUE			((uint32)((uint32)8U << 16U)|(8U + 8U))
-#define ADC2_BNDEND_CONFIGVALUE			(2U)
-
-#define ADC2_G0SAMP_CONFIGVALUE			(1U)
-#define ADC2_G1SAMP_CONFIGVALUE			(1U)
-#define ADC2_G2SAMP_CONFIGVALUE			(1U)
-
-#define ADC2_G0SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
-#define ADC2_G1SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
-#define ADC2_G2SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
-
-#define ADC2_PARCR_CONFIGVALUE			(0x00000005U)
-
 /** 
  *  @defgroup ADC ADC
  *  @brief Analog To Digital Converter Module.