Index: firmware/App/Common.h =================================================================== diff -u -r0595b4b31cef5980bc589ff7ce39a4e97bc81d8d -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Common.h (.../Common.h) (revision 0595b4b31cef5980bc589ff7ce39a4e97bc81d8d) +++ firmware/App/Common.h (.../Common.h) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -14,7 +14,7 @@ #define CAN_MESSAGE_PAYLOAD_SIZE 8 #define FIRMWARE_START_ADDRESS 0x00010000 #define FIRMWARE_CRC_TABLE_ADDRESS 0x10020 ///< The starting address of CRC table for firmware image. -#define SW_UPDATE_FLASH_BUFFER_SIZE 128 +#define SW_UPDATE_FLASH_BUFFER_SIZE 256 #define MASK_OFF_MSB 0x00FF ///< Bits to mask off the most significant byte of a 2-byte word #define MASK_OFF_LSB 0xFF00 ///< Bits to mask off the least significant byte of a 2-byte word #define SHIFT_8_BITS_FOR_BYTE_SHIFT 8 ///< Number of bits to shift in order to shift a byte @@ -78,8 +78,9 @@ SW_UPDATE_TD_UPDATE, // 0x602 SW_UPDATE_DD_UPDATE, // 0x603 SW_UPDATE_RO_UPDATE, // 0x604 - PLACE_HOLDER_TO_REMOVE_CAN, // 0x606 - SW_UPDATE_RESP, // 0x607 + PLACE_HOLDER_TO_REMOVE_CAN, // 0x605 + SW_UPDATE_RESP, // 0x606 + SW_TEST, // 0x607 // TODO remove NUM_OF_SW_UPDATE_MBOXES, } SW_UPDATE_CAN_MAIL_BOX_T; Index: firmware/App/Modes/ModeStandby.c =================================================================== diff -u -r9e2779d825ea7e7b3445fa365f7bc2206fc0613a -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision 9e2779d825ea7e7b3445fa365f7bc2206fc0613a) +++ firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -109,25 +109,26 @@ MODE_STANDBY_STATE_T state = STANDBY_CHECK_FW_AND_FPGA_IMAGES_STATE; BOOL isFirmwareImageValid = FALSE; BOOL isFPGAImageValid = FALSE; - + // TODo timeout and wait for a while prior to transitioning + // TODO why a bad code passes the CRC? _disable_IRQ(); if ( TRUE == isFWCRCTableValid() ) { isFirmwareImageValid = runFWIntegrityTest(); } _enable_IRQ(); - if ( TRUE == isFPGAIDValid() ) + //if ( TRUE == isFPGAIDValid() ) { isFPGAImageValid = TRUE; } - if ( ( TRUE == isFirmwareImageValid ) && ( TRUE == isFPGAImageValid ) ) - { + //if ( ( TRUE == isFirmwareImageValid ) && ( TRUE == isFPGAImageValid ) ) + //{ // All good, jump to application - jumpToApplication(); - } - else + // jumpToApplication(); + //} + //else { // TODO do we need to try a few times prior to tansitioning to Idle? Index: firmware/App/Services/Download.c =================================================================== diff -u -r0595b4b31cef5980bc589ff7ce39a4e97bc81d8d -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/Download.c (.../Download.c) (revision 0595b4b31cef5980bc589ff7ce39a4e97bc81d8d) +++ firmware/App/Services/Download.c (.../Download.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -5,6 +5,8 @@ * Author: fw */ +#include "can.h" // TODO remove for testing only + #include // For memcpy and memset #include "CommBuffers.h" @@ -48,6 +50,10 @@ static SW_UPDATE_CMD_T SWUpdateCommandState; static SW_UPDATE_CAN_MAIL_BOX_T thisStackMailBox; +static U32 REMOVETHEVAR = 0; +static U08 REMOVETESTBUFFER[ 256 ]; +static U32 sizeToWrite; + static void processIncomingCmdMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox ); static void processIncomingUpdateMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox ); static void prepareResponseMessage( U08 respOfMsgID, ACK_NACK_STATUS_T ackNack, SW_UPDATE_RESP_STATUS_T* respBuffer ); @@ -96,7 +102,7 @@ ACK_NACK_STATUS_T ackStatus = NACK; U32 calcCRC = 0; U08 msgID = SWUpdateCmdStatus.msgID; - SW_UPDATE_DESINTATION_T dest = (SW_UPDATE_DESINTATION_T)( SWUpdateCmdStatus.updateCmd >> SHIFT_BITS_TO_GET_TARGET ); + SW_UPDATE_DESINTATION_T dest = (SW_UPDATE_DESINTATION_T)( SWUpdateCmdStatus.updateCmd >> SHIFT_BITS_TO_GET_TARGET ); // TODO add more logic for other stacks calcCRC = crc32( calcCRC, (U08*)&SWUpdateCmdStatus, MAX_CRC_CALC_DATA_SIZE ); hasCRCPassed = ( SWUpdateCmdStatus.msgCRC == calcCRC ? TRUE : FALSE ); @@ -165,7 +171,7 @@ prepareResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus, &resp ); status = sendAckNackStatusFromFirmware( (U08*)&resp ); // TODO do we have to retry if send failed? clearCommBuffer( mailBox ); // TODo does this need to be here? How about resync? - clearSWUpdateBuffer(); + //clearSWUpdateBuffer(); // TODO uncomment } } @@ -203,19 +209,53 @@ { ACK_NACK_STATUS_T ackStatus = NACK; - if ( FPGA_UPDATE_READY == getFPGAFlashState() ) + //if ( FPGA_UPDATE_READY == getFPGAFlashState() ) { if ( SWUpdateRCVStatus.cyberIndex != SW_UPDATE_FINAL_MSG_INDEX ) { U08 removeThis; + U08 index = 0; + U32 counter; + U08 test[8]; + sizeToWrite = SW_UPDATE_FLASH_BUFFER_SIZE; + BOOL done = FALSE; - for ( removeThis = 0; removeThis < SW_UPDATE_FLASH_BUFFER_SIZE; removeThis++ ) + /*for ( removeThis = 0; removeThis < SW_UPDATE_FLASH_BUFFER_SIZE; removeThis++ ) { + test[ index ] = SWUpdateRCVStatus.SWUpdateBuffer[removeThis]; + if ( index == 7 ) + { + canTransmit( canREG1, (U32)SW_TEST, test ); // Transmit the FPGA back up to make sure we totally received what we sent + for ( counter = 0; counter < 6000; counter++ ) {} + index = 0; + } + else + { + index += 1; + } + // TODO this is temporary until the ROTTING is removed from the APP - SWUpdateRCVStatus.SWUpdateBuffer[ removeThis ] = 0xFF & ( SWUpdateRCVStatus.SWUpdateBuffer[removeThis] - 27 ); + // SWUpdateRCVStatus.SWUpdateBuffer[ removeThis ] = 0xFF & ( SWUpdateRCVStatus.SWUpdateBuffer[removeThis] - 27 ); + }*/ + // 3192290 + // 1596144 + if ( ( 1596144 - REMOVETHEVAR < SW_UPDATE_FLASH_BUFFER_SIZE ) && ( REMOVETHEVAR != 0 ) ) + { + sizeToWrite = 1596144 - REMOVETHEVAR; + REMOVETHEVAR += sizeToWrite; + done = TRUE; } + else + { + REMOVETHEVAR += SW_UPDATE_FLASH_BUFFER_SIZE; + } - signalFPGAToWriteToFlash( SWUpdateRCVStatus.SWUpdateBuffer, sizeof( SWUpdateRCVStatus.SWUpdateBuffer ) ); + memcpy( REMOVETESTBUFFER, SWUpdateRCVStatus.SWUpdateBuffer, sizeToWrite); + signalFPGAToWriteToFlash( SWUpdateRCVStatus.SWUpdateBuffer, sizeToWrite ); + if ( TRUE == done ) + { + signalFPGAToSelfConfigure(); + } } } Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r0595b4b31cef5980bc589ff7ce39a4e97bc81d8d -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 0595b4b31cef5980bc589ff7ce39a4e97bc81d8d) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -98,7 +98,7 @@ typedef struct { U16 fpgaJobAddress; - U08 fpgaJobSize; + U16 fpgaJobSize; U08* fpgaWriteStartAddress; U08 fpgaIsJobWrite; } FPGA_JOB_SPECS_T; @@ -149,8 +149,10 @@ static U08 fpgaUpdateRegisterStatus; static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; static FPGA_FLASH_STATUS_T fpgaFlashStatus; +static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; +static U32 fpgaDataLenToWrite; -static U32 TESTTIMEREMOVE; +static U32 TESTREMOVE = 0; // TODO remove static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF }; // TODO update with the real FPGA IDs static const U16 DISABLE_UPDATE_REG_CMD = 5; // TODO what is this value? 0? @@ -169,7 +171,7 @@ { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_ERASE_FIFO_STATUS { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FLASH_READY_STATUS { FPGA_FIFO_COUNT_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FIFO_COUNT - { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaWriteCmdBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA + { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; @@ -192,6 +194,7 @@ static void resetFPGACommFlags( void ); static void enqueue( FPGA_JOBS_T job ); static void dequeue( void ); +static BOOL isQueueFull( void ); static FPGA_STATE_T handleFPGAIdleState( void ); @@ -290,28 +293,42 @@ void signalFPGAToPrepareForUpdate( void ) { - enqueue( FPGA_RESET_FLASH ); - enqueue( FPGA_ERASE_FIFO ); - enqueue( FPGA_ENABLE_FLASH ); - enqueue( FPGA_CHECK_ERASE_FIFO_STATUS ); + if ( FALSE == isQueueFull() ) + { + //enqueue( FPGA_RESET_FLASH ); + //enqueue( FPGA_ERASE_FIFO ); + enqueue( FPGA_ENABLE_FLASH ); + //enqueue( FPGA_CHECK_ERASE_FIFO_STATUS ); + } } void signalFPGAToWriteToFlash( U08* data, U32 len ) { - enqueue( FPGA_CHECK_FLASH_READY_STATUS ); - enqueue( FPGA_CHECK_FIFO_COUNT ); - enqueue( FPGA_FLASH_WRITE_DATA ); - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + if ( FALSE == isQueueFull() ) + { + memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); - memcpy( fpgaWriteCmdBuffer, data, len ); + //enqueue( FPGA_CHECK_FLASH_READY_STATUS ); + //enqueue( FPGA_CHECK_FIFO_COUNT ); + enqueue( FPGA_FLASH_WRITE_DATA ); + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + fpgaDataLenToWrite = len; + memcpy( fpgaDataToWriteBuffer, data, len ); - fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_BUSY; + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_BUSY; + } } +void signalFPGAToSelfConfigure( void ) +{ + if ( FALSE == isQueueFull() ) + { + enqueue( FPGA_SELF_CONFIGURE ); + } +} + // ********** private functions ********** static void initDMA( void ) @@ -490,10 +507,12 @@ U16 remFIFOCount = 0; BOOL isStatusOk = FALSE; - remFIFOCount = FPGA_FIFO_COUNT_MASK & MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], - fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); - remFIFOCount = FPGA_FIFO_SIZE_BYTES - remFIFOCount; + U16 word = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], + fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); + U16 test = FPGA_FIFO_COUNT_MASK & word; + remFIFOCount = FPGA_FIFO_SIZE_BYTES - test; + if ( remFIFOCount >= SW_UPDATE_FLASH_BUFFER_SIZE ) { isStatusOk = TRUE; @@ -640,6 +659,18 @@ _enable_IRQ(); } +static BOOL isQueueFull( void ) +{ + BOOL isFull = FALSE; + + if ( fpgaJobsQStatus.fpgaJobsQueueCount >= ( QUEUE_MAX_SIZE - 1 ) ) + { + isFull = TRUE; + } + + return isFull; +} + static FPGA_STATE_T handleFPGAIdleState( void ) { FPGA_STATE_T state = FPGA_IDLE_STATE; @@ -651,6 +682,13 @@ state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); } + // TODo remove + if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob ) + { + BOOL test = FALSE; + } + // TODo remove + return state; } @@ -659,18 +697,31 @@ FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; U16 crc = 0; U16 jobAddress = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobAddress; - U08 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U16 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + + if ( ( fpgaDataLenToWrite != SW_UPDATE_FLASH_BUFFER_SIZE ) && ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) ) + { + jobSize = (U16)fpgaDataLenToWrite; + } + + // TODO remove + if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) + { + BOOL Test = FALSE; + } + // TODO remove + U08* value2Write = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaWriteStartAddress; - U08 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; - U08 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; + U16 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; + U16 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; memcpy( &fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ], value2Write, jobSize ); // Construct bulk read command to read sensor data registers starting at address 8 fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); - fpgaWriteCmdBuffer[ 3 ] = jobSize; + fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + jobSize ); fpgaWriteCmdBuffer[ firstCRCIndex ] = GET_MSB_OF_WORD( crc ); fpgaWriteCmdBuffer[ secondCRCIndex ] = GET_LSB_OF_WORD( crc ); @@ -686,8 +737,6 @@ startDMAReceiptOfWriteResp(); startDMAWriteCmd(); - TESTTIMEREMOVE = getMSTimerCount(); - return state; } @@ -707,21 +756,22 @@ // Does the FPGA response CRC checkout? if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) ) { - if ( TRUE == didTimeout( TESTTIMEREMOVE, 3000) ) + if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) // TODO REMOVE { - // CRC passed - state = FPGA_IDLE_STATE; - memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO remove - + TESTREMOVE += 1; //fpgaDataLenToWrite; + //countRemove += 1; } + + // CRC passed + state = FPGA_IDLE_STATE; } else { // TODO error handling } } - // memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this + memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } return state; Index: firmware/App/Services/FPGA.h =================================================================== diff -u -r0595b4b31cef5980bc589ff7ce39a4e97bc81d8d -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/FPGA.h (.../FPGA.h) (revision 0595b4b31cef5980bc589ff7ce39a4e97bc81d8d) +++ firmware/App/Services/FPGA.h (.../FPGA.h) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -22,5 +22,6 @@ void signalFPGAToPrepareForUpdate( void ); void signalFPGAToWriteToFlash( U08* data, U32 len ); +void signalFPGAToSelfConfigure( void ); #endif Index: firmware/App/Services/Interrupts.c =================================================================== diff -u -r893caf9f58a08a2bd31068806e09603041d64add -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/Interrupts.c (.../Interrupts.c) (revision 893caf9f58a08a2bd31068806e09603041d64add) +++ firmware/App/Services/Interrupts.c (.../Interrupts.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -35,7 +35,6 @@ return returnValue; } - void rtiNotification( uint32 notification ) { switch ( notification ) Index: firmware/App/Services/NVDataMgmt.c =================================================================== diff -u -rf100557efc2f7916054a63bbafb187d8017914d0 -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/NVDataMgmt.c (.../NVDataMgmt.c) (revision f100557efc2f7916054a63bbafb187d8017914d0) +++ firmware/App/Services/NVDataMgmt.c (.../NVDataMgmt.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -163,11 +163,11 @@ U08 bytesWritten = 0; U32 startAddress = SWUpdateFlashStatus.currentWriteAddress; - for ( removeThis = 0; removeThis < SW_UPDATE_FLASH_BUFFER_SIZE; removeThis++ ) - { - // TODO this is temporary until the ROTTING is removed from the APP - data[ removeThis ] = 0xFF & ( data[removeThis] - 27 ); - } + //for ( removeThis = 0; removeThis < SW_UPDATE_FLASH_BUFFER_SIZE; removeThis++ ) + //{ + // TODO this is temporary until the ROTTING is removed from the APP + // data[ removeThis ] = 0xFF & ( data[removeThis] - 27 ); + //} memcpy( dataRead2Verify, data, SW_UPDATE_FLASH_BUFFER_SIZE ); Index: firmware/BL.dil =================================================================== diff -u -rf100557efc2f7916054a63bbafb187d8017914d0 -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/BL.dil (.../BL.dil) (revision f100557efc2f7916054a63bbafb187d8017914d0) +++ firmware/BL.dil (.../BL.dil) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -1,4 +1,4 @@ -# RM46L852PGE 08/15/24 10:42:26 +# RM46L852PGE 09/10/24 15:28:09 # ARCH=RM46L852PGE # @@ -3852,7 +3852,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 @@ -4503,7 +4503,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 @@ -4524,7 +4524,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000080 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 @@ -4946,7 +4946,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000001 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF @@ -5249,7 +5249,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000800 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 Index: firmware/source/can.c =================================================================== diff -u -rf2652e85c8676d0356fea2690cfd9cac716ca795 -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/source/can.c (.../can.c) (revision f2652e85c8676d0356fea2690cfd9cac716ca795) +++ firmware/source/can.c (.../can.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -297,6 +297,25 @@ canREG1->IF2CMD = (uint8) 0xF8U; canREG1->IF2NO = 6U; + /** - Initialize message 7 + * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF1 control byte + * - Set IF1 message number + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x607U & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 7U; + /** - Setup IF1 for data transmission * - Wait until IF1 is ready for use * - Set IF1 control byte