Index: firmware/App/Common.h =================================================================== diff -u -rba60692a9ecaf59cb5cb8490f4276917f43bcd01 -r3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4 --- firmware/App/Common.h (.../Common.h) (revision ba60692a9ecaf59cb5cb8490f4276917f43bcd01) +++ firmware/App/Common.h (.../Common.h) (revision 3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4) @@ -8,14 +8,16 @@ #ifndef __COMMON_H__ #define __COMMON_H__ -#define NUM_OF_FW_STACKS 3 +#define NUM_OF_FW_STACKS 3 #define FIRMWARE_START_ADDRESS 0x00010000 #define FIRMWARE_CRC_TABLE_ADDRESS 0x10020 ///< The starting address of CRC table for firmware image. #define SW_UPDATE_FLASH_BUFFER_SIZE 128 #define MASK_OFF_MSB 0x00FF ///< Bits to mask off the most significant byte of a 2-byte word #define MASK_OFF_LSB 0xFF00 ///< Bits to mask off the least significant byte of a 2-byte word #define SHIFT_8_BITS_FOR_BYTE_SHIFT 8 ///< Number of bits to shift in order to shift a byte +#define MASK_OFF_NIBBLE_MSB 0x0F ///< Bits to mask off the most significant nibble of a byte + #define GET_LSB_OF_WORD(w) ((U08)((w) & MASK_OFF_MSB)) ///< Macro returns the least signficant byte of a 2-byte word #define GET_MSB_OF_WORD(w) ((U08)(((w) >> SHIFT_8_BITS_FOR_BYTE_SHIFT) & MASK_OFF_MSB)) ///< Macro returns the most signficant byte of a 2-byte word #define MAKE_WORD_OF_BYTES(h, l) ((((U16)(h) << SHIFT_8_BITS_FOR_BYTE_SHIFT) & MASK_OFF_LSB) | ((U16)(l) & MASK_OFF_MSB)) ///< Macro merges two bytes into a 2-byte word Index: firmware/App/Modes/ModeUpdate.c =================================================================== diff -u -r9af6fc3e5afc442a877bd5e23ecfa6872a3ad5a4 -r3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4 --- firmware/App/Modes/ModeUpdate.c (.../ModeUpdate.c) (revision 9af6fc3e5afc442a877bd5e23ecfa6872a3ad5a4) +++ firmware/App/Modes/ModeUpdate.c (.../ModeUpdate.c) (revision 3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4) @@ -84,7 +84,6 @@ return state; } - static MODE_SW_UPDATE_STATE_T handleUpdateModeVerifyState( void ) { MODE_SW_UPDATE_STATE_T state = SW_UPDATE_VERIFY_STATE; Index: firmware/App/Services/CommBuffers.c =================================================================== diff -u -rfc4f469fe234371e8f2b9a0625acc66faa6899de -r3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4 --- firmware/App/Services/CommBuffers.c (.../CommBuffers.c) (revision fc4f469fe234371e8f2b9a0625acc66faa6899de) +++ firmware/App/Services/CommBuffers.c (.../CommBuffers.c) (revision 3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4) @@ -14,7 +14,9 @@ #define CAN_MESSAGE_PAYLOAD_SIZE 8 #define SW_UPDATE_FINAL_MSG_INDEX 0xFFFF +#define SHIFT_BITS_TO_GET_TARGET 4 + typedef struct { U32 SWUpdateFrameCount; @@ -99,7 +101,6 @@ memcpy( status, &SWUpdateBufferStatus, sizeof( SW_UPDATE_BUFFER_STATUS_T ) ); } - void getSWUpdateBuffer( U08* data ) { memcpy( data, SWUpdateRcvStatus.SWUpdateBuffer, sizeof( SWUpdateRcvStatus.SWUpdateBuffer ) ); Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rba60692a9ecaf59cb5cb8490f4276917f43bcd01 -r3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision ba60692a9ecaf59cb5cb8490f4276917f43bcd01) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 3a0dc476f0f42bb7ebadc7d6109a0b5b6581cce4) @@ -40,6 +40,7 @@ #define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. #define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. #define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. +#define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. #define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) #define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. @@ -48,6 +49,9 @@ #define UPDATE_REQUESTED_VALUE 1 +#define FPGA_ERASE_FIFO_CMD_OK ( 1 << 11 ) +#define FPGA_FLASH_STATUS_OK ( 1 << 15 ) + typedef enum { FPGA_COMM_IDLE = 0, @@ -66,9 +70,11 @@ FPGA_RESET_FLASH, FPGA_ERASE_FIFO, FPGA_ENABLE_FLASH, - FPGA_CHECK_FLASH_STATUS, + FPGA_CHECK_ERASE_FIFO_STATUS, + FPGA_CHECK_FLASH_READY_STATUS, FPGA_CHECK_FIFO_COUNT, - FPGA_FLASH_UPDATE_DATA, + FPGA_FLASH_WRITE_DATA, + FPGA_SELF_CONFIGURE, NUM_OF_FPGA_JOBS, } FPGA_JOBS_T; @@ -82,6 +88,15 @@ NUM_OF_FPGA_STATES } FPGA_STATE_T; +typedef enum +{ + FPGA_UPDATE_NOT_STARTED = 0, + FPGA_UPDATE_INITIALIZE_FLASH, + FPGA_UPDATE_FLASH_IN_PROG, + FPGA_UPDATE_FINISH_FLASH, + NUM_OF_FPGA_FLASH_STATE, +} FPGA_FLASH_STATE_T; // TODO remove? + #pragma pack(push,1) typedef struct { @@ -102,6 +117,14 @@ FPGA_COMM_STATE_T fpgaCommWrite; } FPGA_JOBS_Q_STATUS_T; +typedef struct +{ + BOOL isFlashErased; + BOOL isFlashReady; + U16 FIFOCount; + U32 startTime; +} FPGA_FLASH_STATUS_T; + /// Record structure for FPGA header read. typedef struct { @@ -135,20 +158,25 @@ static const U08 FPGA_RESET_FLASH_CMD = 0x01; static const U08 FPGA_ERASE_FIFO_CMD = 0x08; static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; +static const U08 FPGA_SELF_CONFIG_CMD = 0x03; + static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // FPGA_READ_UPDATE_REG { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), (U08*)&DISABLE_UPDATE_REG_CMD, TRUE }, // FPGA_WRITE_UPDATE_REG { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH - { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FLASH_STATUS + { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_ERASE_FIFO_STATUS + { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FLASH_READY_STATUS { FPGA_FIFO_COUNT_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FIFO_COUNT - { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaWriteCmdBuffer, TRUE } // FPGA_FLASH_UPDATE_DATA + { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaWriteCmdBuffer, TRUE }, // FPGA_FLASH_UPDATE_DATA + { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; static void initDMA( void ); static void consumeUnexpectedData( void ); +static void processFPGAReceivedData( void ); static void setupDMAForReadResp( U32 bytes2Receive ); static void setupDMAForReadCmd( U32 bytes2Transmit ); @@ -234,9 +262,11 @@ { BOOL status = FALSE; - if ( FPGA_IDLE_STATE == fpgaState ) + if ( ( FPGA_IDLE_STATE == fpgaState ) && ( UPDATE_REQUESTED_VALUE == fpgaUpdateRegisterStatus ) ) { - status = ( UPDATE_REQUESTED_VALUE == fpgaUpdateRegisterStatus ? TRUE : FALSE ); + status = TRUE; + fpgaUpdateRegisterStatus = 0; + enqueue( FPGA_WRITE_UPDATE_REG ); } return status; @@ -351,7 +381,35 @@ } } +static void processFPGAReceivedData( void ) +{ + // Capture the read values + switch( fpgaJobsQStatus.fpgaCurrentJob ) + { + case FPGA_READ_HEADER: + memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); + break; + case FPGA_READ_UPDATE_REG: + fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; + break; + + case FPGA_CHECK_ERASE_FIFO_STATUS: + break; + + case FPGA_CHECK_FLASH_READY_STATUS: + break; + + case FPGA_CHECK_FIFO_COUNT: + break; + + default: + // Do nothing + break; + } +} + + static void setupDMAForReadResp( U32 bytes2Receive ) { // Verify # of bytes does not exceed buffer length @@ -609,18 +667,8 @@ // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { - // Capture the read values - switch( fpgaJobsQStatus.fpgaCurrentJob ) - { - case FPGA_READ_HEADER: - memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); - break; + processFPGAReceivedData(); - case FPGA_READ_UPDATE_REG: - fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; - break; - } - fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_IDLE; state = FPGA_IDLE_STATE; }