Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r3e9328290bdbc18a940935bd7f7c720ca8432b1d -r21aec35b34a19514e0e00e8596e9884916ab91f1 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 3e9328290bdbc18a940935bd7f7c720ca8432b1d) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 21aec35b34a19514e0e00e8596e9884916ab91f1) @@ -25,6 +25,8 @@ #include "Comm.h" #include "Compatible.h" #include "FPGA.h" +#include "NVDataMgmt.h" +#include "OperationModes.h" #include "PersistentAlarm.h" #include "SystemCommMessages.h" #include "Utilities.h" @@ -84,7 +86,11 @@ #define CONCENTRATE_CAP_SWITCH_MASK 0x10 ///< Concentrate cap switch bit mask #define DIALYSATE_CAP_SWITCH_MASK 0x20 ///< Dialysate cap switch bit mask. #define FPGA_POWER_OUT_TIMEOUT_MS ( 2 * MS_PER_SECOND ) ///< FPGA power out timeout in milliseconds. -#define FPGA_GPIO_POWER_STATUS_PIN 7 ///< FPGA GPIO power status pin +#define FPGA_GPIO_POWER_STATUS_PIN 7 ///< FPGA GPIO power status pin. +#define FPGA_READ_V3_START_BYTE_NUM 156 ///< FPGA V3 read sensors start byte number. +#define FPGA_READ_V3_END_BYTE_NUM 410 ///< FPGA V3 read sensors end byte number. +/// FPGA size of V3 read bytes. +#define FPGA_SIZE_OF_V3_READ_BYTES ( FPGA_READ_V3_END_BYTE_NUM - FPGA_READ_V3_START_BYTE_NUM ) // FPGA header struct. #pragma pack(push,1) @@ -323,6 +329,7 @@ static FPGA_HEADER_T fpgaHeader; ///< FPGA header structure. static DG_FPGA_SENSORS_T fpgaSensorReadings; ///< DG FPGA sensors structure. static FPGA_ACTUATORS_T fpgaActuatorSetPoints; ///< FPGA actuator set points structure. +static U08 fpgaReadByteSize; ///< FPGA read byte size. // ********** private function prototypes ********** @@ -369,6 +376,10 @@ memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); + // Assume the read byte size is set for V3 since V3 contains less number of bytes. + // Once the V3 or DVT build switch is set resize the number of bytes to read. + fpgaReadByteSize = FPGA_SIZE_OF_V3_READ_BYTES; + // enable interrupt notifications for FPGA serial port sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); @@ -535,6 +546,19 @@ *************************************************************************/ void execFPGAIn( void ) { + fpgaReadByteSize = sizeof( DG_FPGA_SENSORS_T ); + +/*#ifndef _RELEASE_ + if( ( SW_CONFIG_ENABLE_VALUE != getSoftwareConfigStatus( SW_CONFIG_ENABLE_V3_SYSTEM ) ) && ( getCurrentOperationMode() != DG_MODE_INIT ) ) + { + fpgaReadByteSize = + } + else + { + + } +#endif*/ + // FPGA incoming state machine switch ( fpgaState ) { @@ -724,7 +748,7 @@ fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_WRITE_START_ADDR ); - fpgaWriteCmdBuffer[ 3 ] = sizeof(FPGA_ACTUATORS_T); + fpgaWriteCmdBuffer[ 3 ] = sizeof( FPGA_ACTUATORS_T ); memcpy( &( fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ] ), &fpgaActuatorSetPoints, sizeof( FPGA_ACTUATORS_T ) ); crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) ); fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) ] = GET_MSB_OF_WORD( crc ); @@ -734,7 +758,7 @@ fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( FPGA_BULK_READ_START_ADDR ); - fpgaReadCmdBuffer[ 3 ] = sizeof(DG_FPGA_SENSORS_T); + fpgaReadCmdBuffer[ 3 ] = sizeof( DG_FPGA_SENSORS_T ); crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );