Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r55c11d87989243f1d755d06910529214db4f7312 -r83b12013a84403fe4d7d6f70b516d623bfb2fcfd
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 55c11d87989243f1d755d06910529214db4f7312)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 83b12013a84403fe4d7d6f70b516d623bfb2fcfd)
@@ -835,44 +835,58 @@
                 checkFPGACommFailure();
             }
         }
+        else
+        {
+            // Not an ACK
+            checkFPGACommFailure();
+        }
     }
     else
     {
         // Timeout - communication error
         checkFPGACommFailure();
     }
 
-    // if bulk read command is ACK'd, collect the readings
-    if ( TRUE == fpgaReadCommandResponseReceived )
+    /* If the write command response (ACK) was not received, the read response
+     * was not issued.  If this is the case the read response will also
+     * timeout.  For FPGA V&V testing this will cause two timeouts to occur.
+     * The V&V expectation is that when the timeout test is executed a
+     * single timeout will occur.
+     */
+    if ( TRUE == fpgaWriteCommandResponseReceived )
     {
-        // did FPGA Ack the read command?
-        if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
+        // if bulk read command is ACK'd, collect the readings
+        if ( TRUE == fpgaReadCommandResponseReceived )
         {
-            U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize;
-            U32 crcPos  = rspSize;
-            U16 crc     = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
-
-            // does the FPGA response CRC check out?
-            if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
+            // did FPGA ACK the read command?
+            if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
             {
-                // capture the read values
-                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize );
-                result = FPGA_STATE_WRITE_ALL_ACTUATORS;
+                U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize;
+                U32 crcPos  = rspSize;
+                U16 crc     = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
+
+                // does the FPGA response CRC check out?
+                if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
+                {
+                    // capture the read values
+                    memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize );
+                    result = FPGA_STATE_WRITE_ALL_ACTUATORS;
+                }
+                else // bad CRC
+                {
+                    checkFPGACommFailure();
+               }
             }
-            else // bad CRC
+            else // read command was NAK'd
             {
                 checkFPGACommFailure();
-           }
+            }
         }
-        else // read command was NAK'd
+        else // no response to read command
         {
             checkFPGACommFailure();
         }
     }
-    else // no response to read command
-    {
-        checkFPGACommFailure();
-    }
 
     // There should not be any data received at this time
     consumeUnexpectedData();