Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r67021fbc633259e8e1bce76749dbef7d0cb51998 -r94a190522ce398399c7b93c59f788d7666ec0060
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 67021fbc633259e8e1bce76749dbef7d0cb51998)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 94a190522ce398399c7b93c59f788d7666ec0060)
@@ -1,18 +1,18 @@
 
 /**************************************************************************
 *
-* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+* Copyright (c) 2019-2021 Diality Inc. - All Rights Reserved.
 *
 * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
 * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
 *
-* @file FPGA.c
+* @file    FPGA.c
 *
-* @author (last) Peman Montazemi
-* @date (last) 09-Mar-2021
+* @author  (last)      Dara Navaei
+* @date    (last)      09-Nov-2021
 *
-* @author (original) Dara Navaei
-* @date (original) 05-Nov-2019
+* @author  (original)  Dara Navaei
+* @date    (original)  05-Nov-2019
 *
 ***************************************************************************/
 
@@ -82,8 +82,8 @@
 #define FPGA_FLUIDLEAK_STATE_MASK       0x0004                  ///< Bit mask for fluid leak detector.
 
 #define FLUID_DOOR_SWITCH_MASK          0x08                    ///< Fluid door switch bit mask.
-#define DIALYSATE_CAP_SWITCH_MASK       0x10                    ///< Dialysate cap switch bit mask.
-#define CONCENTRATE_CAP_SWITCH_MASK     0x1A                    ///< Concentrate cap switch bit mask.
+#define CONCENTRATE_CAP_SWITCH_MASK     0x10                    ///< Concentrate cap switch bit mask
+#define DIALYSATE_CAP_SWITCH_MASK       0x20                    ///< Dialysate cap switch bit mask..
 #define FPGA_POWER_OUT_TIMEOUT_MS       ( 2 * MS_PER_SECOND )   ///< FPGA power out timeout in milliseconds.
 #define FPGA_GPIO_POWER_STATUS_PIN      7                       ///< FPGA GPIO power status pin
 
@@ -185,7 +185,17 @@
     U16 fpgaFanOut2Pulse;                   ///< Reg 398. Fan outlet 2 pulse time in 2.5 resolution
     U16 fpgaFanIn3Pulse;                    ///< Reg 400. Fan inlet 3 pulse time in 2.5 resolution
     U16 fpgaFanOut3Pulse;                   ///< Reg 402. Fan outlet 3 pulse time in 2.5 resolution
-    U16 fpgaTimerCount_ms;                  ///< Reg 404.  Internal FPGA timer count in ms.
+    U16 fpgaTimerCount_ms;                  ///< Reg 404. Internal FPGA timer count in ms.
+
+    U16 fpgaADCVccInt;                      ///< Reg 406. Internal FPGA Vcc Voltage.
+    U16 fpgaADCVccAux;                      ///< Reg 408. Internal FPGA Vcc auxiliary voltage.
+    U16 fpgaADCVPVN;                        ///< Reg 410. Internal FPGA VPVN voltage.
+
+    U16 fpgaOpenRegister;                   ///< Reg 412. Open register.
+    U16 fpgaDrainPumpSpeedFeedback;         ///< Reg 414. Drain pump speed feedback.
+    U16 fpgaDrainPumpCurrentFeedback;       ///< Reg 416. Drain pump current feedback.
+
+    U16 fpgaFMPROFlowTemporary;             ///< Reg 418. FMP flow sensor temporary register.
 } DG_FPGA_SENSORS_T;
 
 typedef struct
@@ -1593,6 +1603,19 @@
 
 /*********************************************************************//**
  * @brief
+ * The getFPGAConcentratePumpsFault function gets concentrate pumps fault
+ * reported by FGPA.
+ * @details Inputs: fpgaSensorReadings.fpgaCP1CP2Fault
+ * @details Outputs: none
+ * @return Latest concentrate pumps fault value
+ *************************************************************************/
+U08 getFPGAConcentratePumpsFault( void )
+{
+    return fpgaSensorReadings.fpgaCP1CP2Fault;
+}
+
+/*********************************************************************//**
+ * @brief
  * The getFPGAEmstatOutByte function gets Emstat conductivity sensor output byte.
  * @details Inputs: fpgaSensorReadings.fpgaEmstatOutByte
  * @details Outputs: none