Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r83b12013a84403fe4d7d6f70b516d623bfb2fcfd -r9b1ae2d7327c0b865be12685641dea8668368ac1
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 83b12013a84403fe4d7d6f70b516d623bfb2fcfd)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 9b1ae2d7327c0b865be12685641dea8668368ac1)
@@ -356,10 +356,6 @@
 static DG_FPGA_SENSORS_T    fpgaSensorReadings;                     ///< DG FPGA sensors structure.
 static FPGA_ACTUATORS_T     fpgaActuatorSetPoints;                  ///< FPGA actuator set points structure.
 static U08 fpgaReadByteSize;                                        ///< FPGA read byte size.
-#ifndef DEBUG_ENABLED
-static U16 currentFPGATimerCount_ms;                                ///< Current FPGA timer count in ms.
-static U32 currentTimerCount_ms;                                    ///< Current processor timer count in ms.
-#endif
 
 // ********** private function prototypes **********
 
@@ -379,7 +375,6 @@
 static void startDMAReceiptOfReadResp( void );
 
 static void consumeUnexpectedData( void );
-static void monitorFPGAPowerStatus( void );
 
 static BOOL checkFPGACommFailure( void );
 
@@ -499,9 +494,6 @@
     // there shouldn't be any data pending yet
     consumeUnexpectedData();
 
-    // Initialize the persistent alarm for FPGA power out
-    initPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, FPGA_POWER_OUT_TIMEOUT_MS, FPGA_POWER_OUT_TIMEOUT_MS );
-
     // initialize FPGA clock speed error time windowed count
     initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES_WINDOW_MS);
 
@@ -615,18 +607,14 @@
     }
 
     // if retries for commands exceeds limit or FPGA reports comm error, fault
-#ifdef _RELEASE_
     if ( fpgaSensorReadings.fpgaIOErrorCntProcessor > MAX_COMM_ERROR_RETRIES )
     {
         SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
     }
-#endif
 
     // reset comm flags after processing incoming responses
     resetFPGACommFlags();
 
-    // Check the FPGA power status
-    monitorFPGAPowerStatus();
 }
 
 /*********************************************************************//**
@@ -932,21 +920,20 @@
  * @brief
  * The execFPGAClockSpeedTest function verifies the processor clock speed
  * against the FPGA clock.
- * @details Inputs: fpgaHeader
+ * @details Inputs:  fpgaHeader,
+ *                   window timer TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR
  * @details Outputs: none
- * @return passed, or failed
+ * @return:          none
  *************************************************************************/
 void execFPGAClockSpeedTest( void )
 {
-
-#ifndef DEBUG_ENABLED
     static U16 currentFPGATimerCount_ms = 0;
-    static U32 currentTimerCount_ms = 0;
+    static U32 currentTimerCount_ms     = 0;
 
     U16 const newFPGATimerCount_ms = getFPGATimerCount();
-    U32 const newTimerCount_ms = getMSTimerCount();
-    U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
-    U32 const diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
+    U32 const newTimerCount_ms     = getMSTimerCount();
+    U32 const diffFPGATimerCount   = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
+    U32 const diffTimerCount       = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
 
     if ( getCurrentOperationMode() != DG_MODE_INIT )
     {
@@ -960,8 +947,7 @@
     }
 
     currentFPGATimerCount_ms = newFPGATimerCount_ms;
-    currentTimerCount_ms = newTimerCount_ms;
-#endif
+    currentTimerCount_ms     = newTimerCount_ms;
 }
 
 /*********************************************************************//**
@@ -1133,22 +1119,6 @@
 
 /*********************************************************************//**
  * @brief
- * The monitorFPGAPowerStatus function monitors the status of the FPGA power source.
- * @details Inputs: none
- * @details Outputs: none
- * @return none
- *************************************************************************/
-static void monitorFPGAPowerStatus( void )
-{
-    // If the GIO bit returned a 0 it mean the power is out, otherwise the power is not out
-    BOOL isPowerOut = ( TRUE == (BOOL)gioGetBit( gioPORTA, FPGA_GPIO_POWER_STATUS_PIN ) ? FALSE : TRUE );
-
-    // TODO check to make sure alarm is not raised when the power is good
-    checkPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, isPowerOut, 0, FPGA_POWER_OUT_TIMEOUT_MS );
-}
-
-/*********************************************************************//**
- * @brief
  * The setFPGAValveStates function sets the DG valve states with a 16-bit
  * set of states - one bit per valve, with a 1 meaning "energized" and a 0
  * meaning "de-energized".  The bit positions for these bit states are as follows: