Index: firmware/.cproject
===================================================================
diff -u -r33c227865b5060922524162df4add41e4536a6d5 -r80f120f475bbd71c798c2a012633aab91cf0b5f0
--- firmware/.cproject	(.../.cproject)	(revision 33c227865b5060922524162df4add41e4536a6d5)
+++ firmware/.cproject	(.../.cproject)	(revision 80f120f475bbd71c798c2a012633aab91cf0b5f0)
@@ -48,8 +48,9 @@
 									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/include}"/>
 									<listOptionValue builtIn="false" value="${CG_TOOL_ROOT}/include"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DEFINE.2117990509" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DEFINE" valueType="definedSymbols">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DEFINE.2117990509" name="Pre-define NAME (--define, -D)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DEFINE" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="__TI_VIM_128CH__"/>
+									<listOptionValue builtIn="false" value="BOARD_WITH_NO_HARDWARE"/>
 									<listOptionValue builtIn="false" value="WITH_BOOTLOADER"/>
 									<listOptionValue builtIn="false" value="DEBUG_ENABLED"/>
 									<listOptionValue builtIn="false" value="_DG_"/>
Index: firmware/DG.dil
===================================================================
diff -u -r53110a8d810e392e8f75cf0bf85a3ec07927e846 -r80f120f475bbd71c798c2a012633aab91cf0b5f0
--- firmware/DG.dil	(.../DG.dil)	(revision 53110a8d810e392e8f75cf0bf85a3ec07927e846)
+++ firmware/DG.dil	(.../DG.dil)	(revision 80f120f475bbd71c798c2a012633aab91cf0b5f0)
@@ -1,4 +1,4 @@
-# RM46L852PGE 07/27/22 16:12:46
+# RM46L852PGE 05/05/23 14:16:52
 # 
 ARCH=RM46L852PGE
 # 
@@ -41,7 +41,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xfcffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0xFCFFFFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0
@@ -89,7 +89,7 @@
 DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE
 DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63ffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x63FFFFFF
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0
@@ -105,7 +105,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18
 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATEVALUE.VALUE=0x5
 DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0
@@ -130,7 +130,7 @@
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003fffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003FFFFF
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=0
@@ -204,7 +204,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1
 DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203fffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x203FFFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0
@@ -240,7 +240,7 @@
 DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt
 DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1
-DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN4_RAMPARITYCHECK_ENA.VALUE=0
@@ -351,8 +351,8 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC
 DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE
-DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1
-DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1
+DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE
@@ -473,7 +473,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16
 DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xf07fffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0
@@ -506,7 +506,7 @@
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843ffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0x0843FFFF
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ
@@ -561,7 +561,7 @@
 DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xffffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xFFFFFFFF
 DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ
@@ -629,7 +629,7 @@
 DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
 DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002b400
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802FFFF
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0
@@ -707,7 +707,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE
 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1
-DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000
 DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0
@@ -849,7 +849,7 @@
 DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xfe0001ff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xFE0001FF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=0
@@ -895,7 +895,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4
 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87ffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_GB
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ
@@ -949,7 +949,7 @@
 DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_SHARED
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803ffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803FFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ
@@ -1056,7 +1056,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104
-DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xffffffff
+DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0xFFFFFFFF
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc
Index: firmware/source/sys_link.cmd
===================================================================
diff -u -r3d211bbf5607fb42f003d074caa58f75069774e9 -r80f120f475bbd71c798c2a012633aab91cf0b5f0
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 3d211bbf5607fb42f003d074caa58f75069774e9)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 80f120f475bbd71c798c2a012633aab91cf0b5f0)
@@ -1,36 +1,36 @@
 /*----------------------------------------------------------------------------*/
 /* sys_link.cmd                                                               */
 /*                                                                            */
-/*
-* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright
+*    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
@@ -119,15 +119,15 @@
 SECTIONS
 {
     .intvecs : {} > VECTORS
-    .text    : {} > FLASH0
-    .const   : {} > FLASH0
-    .cinit   : {} > FLASH0
-    .pinit   : {} > FLASH0
+    .text    : {} > FLASH0 
+    .const   : {} > FLASH0 
+    .cinit   : {} > FLASH0 
+    .pinit   : {} > FLASH0 
     .bss     : {} > RAM
     .data    : {} > RAM
     .sysmem  : {} > RAM
+    
 
-
 /* USER CODE BEGIN (4) */
 #endif
 /* Override Sections with CRCs here */
Index: firmware/source/sys_mpu.asm
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -r80f120f475bbd71c798c2a012633aab91cf0b5f0
--- firmware/source/sys_mpu.asm	(.../sys_mpu.asm)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/sys_mpu.asm	(.../sys_mpu.asm)	(revision 80f120f475bbd71c798c2a012633aab91cf0b5f0)
@@ -181,16 +181,6 @@
         mcr   p15, #0,    r0, c6, c1, #2
 
 
-        ; Enable mpu background region
-        mrc   p15, #0, r0,      c1, c0, #0
-        orr   r0,  r0, #0x20000
-        mcr   p15, #0, r0,      c1, c0, #0
-        ; Enable mpu
-        mrc   p15, #0, r0, c1, c0, #0
-        orr   r0,  r0, #1
-        dsb
-        mcr   p15, #0, r0, c1, c0, #0
-        isb
         bx    lr
 
 r1Base  .word 0x00000000
Index: firmware/source/sys_startup.c
===================================================================
diff -u -r33c227865b5060922524162df4add41e4536a6d5 -r80f120f475bbd71c798c2a012633aab91cf0b5f0
--- firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 33c227865b5060922524162df4add41e4536a6d5)
+++ firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 80f120f475bbd71c798c2a012633aab91cf0b5f0)
@@ -1,4 +1,4 @@
-/** @file sys_startup.c
+/** @file sys_startup.c 
 *   @brief Startup Source File
 *   @date 11-Dec-2018
 *   @version 04.07.01
@@ -13,36 +13,36 @@
 *   which are relevant for the Startup.
 */
 
-/*
-* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
-*
-*
-*  Redistribution and use in source and binary forms, with or without
-*  modification, are permitted provided that the following conditions
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright
+*    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the
-*    documentation and/or other materials provided with the
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
@@ -99,7 +99,7 @@
 /* DesignId : STARTUP_DesignId_001 */
 /* Requirements : HL_SR508 */
 void _c_int00(void)
-{
+{    
 /* USER CODE BEGIN (5) */
 /* USER CODE END */
 
@@ -120,26 +120,14 @@
      * by its ECC logic for accesses to program flash or data RAM.
      */
     _coreEnableEventBusExport_();
-/* USER CODE BEGIN (9) */
-/* USER CODE END */
 
-    /* Enable response to ECC errors indicated by CPU for accesses to flash */
-    flashWREG->FEDACCTRL1 = 0x000A060AU;
-
-/* USER CODE BEGIN (10) */
-/* USER CODE END */
-
-    /* Enable CPU ECC checking for ATCM (flash accesses) */
-    _coreEnableFlashEcc_();
-
-
 /* USER CODE BEGIN (11) */
 /* USER CODE END */
 
         /* Workaround for Errata CORTEXR4 66 */
         _errata_CORTEXR4_66_();
-
-        /* Workaround for Errata CORTEXR4 57 */
+    
+        /* Workaround for Errata CORTEXR4 57 */ 
         _errata_CORTEXR4_57_();
 
     /* Reset handler: the following instructions read from the system exception status register
@@ -149,7 +137,7 @@
     /* check for power-on reset condition */
     /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
     if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
-    {
+    {		
 /* USER CODE BEGIN (12) */
         crcREG->PSA_SIGREGL1 = SYS_EXCEPTION;
 /* USER CODE END */
@@ -182,26 +170,26 @@
     /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
     else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
     {
-        /* Reset caused due
+        /* Reset caused due 
          *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
          *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
          */
         /* Check the WatchDog Status register */
         if(WATCHDOG_STATUS != 0U)
         {
-            /* Add user code here to handle watchdog violation. */
+            /* Add user code here to handle watchdog violation. */ 
 /* USER CODE BEGIN (17) */
 /* USER CODE END */
 
-            /* Clear the Watchdog reset flag in Exception Status register */
+            /* Clear the Watchdog reset flag in Exception Status register */ 
             SYS_EXCEPTION = WATCHDOG_RESET;
-
+        
 /* USER CODE BEGIN (18) */
 /* USER CODE END */
         }
         else
         {
-            /* Clear the ICEPICK reset flag in Exception Status register */
+            /* Clear the ICEPICK reset flag in Exception Status register */ 
             SYS_EXCEPTION = ICEPICK_RESET;
 /* USER CODE BEGIN (19) */
 /* USER CODE END */
@@ -229,7 +217,7 @@
     {
         /* Reset caused due to software reset.
         Add user code to handle software reset. */
-
+		
 /* USER CODE BEGIN (22) */
 /* USER CODE END */
 	}
@@ -262,8 +250,8 @@
     /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
         for(;;)
-        {
-        }/* Wait */
+        { 
+        }/* Wait */                 
 /* USER CODE BEGIN (25) */
 #endif
 /* USER CODE END */
@@ -274,66 +262,66 @@
 
     /* Initialize System - Clock, Flash settings with Efuse self check */
     systemInit();
-
+    
     /* Workaround for Errata PBIST#4 */
     errata_PBIST_4();
-
+	
     /* Run a diagnostic check on the memory self-test controller.
      * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
      * The memory self-test is expected to fail. The function ensures that the PBIST controller
      * is capable of detecting and indicating a memory self-test failure.
      */
-    pbistSelfCheck();
-
+    pbistSelfCheck();	
+	
 	/* Run PBIST on STC ROM */
     pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
              ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
-
+    
     /* Wait for PBIST for STC ROM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    {
-    }/* Wait */
-
+    { 
+    }/* Wait */ 
+    
     /* Check if PBIST on STC ROM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
         /* PBIST and STC ROM failed the self-test.
          * Need custom handler to check the memory failure
          * and to take the appropriate next step.
          */
-
+         
         pbistFail();
 
-    }
-
+    }   
+	
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
 
 	/* Run PBIST on PBIST ROM */
     pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
              ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
-
+    
     /* Wait for PBIST for PBIST ROM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    {
-    }/* Wait */
-
+    { 
+    }/* Wait */ 
+    
     /* Check if PBIST ROM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
         /* PBIST and STC ROM failed the self-test.
          * Need custom handler to check the memory failure
          * and to take the appropriate next step.
          */
-
+         
         pbistFail();
 
-    }
-
+    } 
+	
     /* Disable PBIST clocks and disable memory self-test mode */
-    pbistStop();
+    pbistStop();	
 /* USER CODE BEGIN (29) */
 /* USER CODE END */
 
@@ -342,7 +330,7 @@
 
     /* Disable RAM ECC before doing PBIST for Main RAM */
     _coreDisableRamEcc_();
-
+    
     /* Run PBIST on CPU RAM.
      * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
      * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
@@ -357,13 +345,13 @@
     /* Wait for PBIST for CPU RAM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    {
-    }/* Wait */
+    { 
+    }/* Wait */                 
+    
 
-
 /* USER CODE BEGIN (33) */
 /* USER CODE END */
-
+    
     /* Check if CPU RAM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
@@ -373,9 +361,9 @@
          */
 /* USER CODE BEGIN (34) */
 /* USER CODE END */
-
+         
         pbistFail();
-
+        
 /* USER CODE BEGIN (35) */
 /* USER CODE END */
     }
@@ -386,36 +374,16 @@
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
 
-
+    
 /* USER CODE BEGIN (37) */
 /* USER CODE END */
 
-
-    /* Initialize CPU RAM.
-     * This function uses the system module's hardware for auto-initialization of memories and their
-     * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
-     * Hence the value 0x1 passed to the function.
-     * This function will initialize the entire CPU RAM and the corresponding ECC locations.
-     */
-    memoryInit(0x1U);
-
-/* USER CODE BEGIN (38) */
-/* USER CODE END */
-
-    /* Enable ECC checking for TCRAM accesses.
-     * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
-     */
-    _coreEnableRamEcc_();
-
-/* USER CODE BEGIN (39) */
-/* USER CODE END */
-
     /* Start PBIST on all dual-port memories */
     /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
        PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
      */
     pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
-             | (uint32)0x00000000U    /* USB RAM */
+             | (uint32)0x00000000U    /* USB RAM */  
              | (uint32)0x00000800U    /* DMA RAM */
              | (uint32)0x00000200U    /* VIM RAM */
              | (uint32)0x00000040U    /* MIBSPI1 RAM */
@@ -436,28 +404,16 @@
 
 /* USER CODE BEGIN (40) */
 /* USER CODE END */
-
-    /* Test the CPU ECC mechanism for RAM accesses.
-     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
-     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
-     * in the ECC causes a data abort exception. The data abort handler is written to look for
-     * deliberately caused exception and to return the code execution to the instruction
-     * following the one that caused the abort.
-     */
-    checkRAMECC();
-
-/* USER CODE BEGIN (41) */
-/* USER CODE END */
 /* USER CODE BEGIN (43) */
 /* USER CODE END */
 
     /* Wait for PBIST for CPU RAM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    {
-    }/* Wait */
+    { 
+    }/* Wait */                 
+    
 
-
 /* USER CODE BEGIN (44) */
 /* USER CODE END */
 
@@ -474,9 +430,9 @@
          */
 /* USER CODE BEGIN (46) */
 /* USER CODE END */
-
+         
         pbistFail();
-
+        
 /* USER CODE BEGIN (47) */
 /* USER CODE END */
     }
@@ -486,31 +442,31 @@
 
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
-
+    
 /* USER CODE BEGIN (55) */
 /* USER CODE END */
 
     /* Release the MibSPI1 modules from local reset.
      * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
      */
      mibspiREG1->GCR0 = 0x1U;
-
+     
     /* Release the MibSPI3 modules from local reset.
      * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
      */
     mibspiREG3->GCR0 = 0x1U;
-
+    
     /* Release the MibSPI5 modules from local reset.
      * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
      */
     mibspiREG5->GCR0 = 0x1U;
-
+    
 /* USER CODE BEGIN (56) */
 /* USER CODE END */
 
     /* Enable parity on selected RAMs */
     enableParity();
-
+    
     /* Initialize all on-chip SRAMs except for MibSPIx RAMs
      * The MibSPIx modules have their own auto-initialization mechanism which is triggered
      * as soon as the modules are brought out of local reset.
@@ -535,62 +491,62 @@
 
     /* Disable parity */
     disableParity();
-
+    
     /* Test the parity protection mechanism for peripheral RAMs
        NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
                  Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
     */
 
 /* USER CODE BEGIN (57) */
 /* USER CODE END */
-
+     
     het1ParityCheck();
-
+    
 /* USER CODE BEGIN (58) */
 /* USER CODE END */
 
     htu1ParityCheck();
-
+    
 /* USER CODE BEGIN (59) */
 /* USER CODE END */
 
     het2ParityCheck();
-
+    
 /* USER CODE BEGIN (60) */
 /* USER CODE END */
 
     htu2ParityCheck();
-
+    
 /* USER CODE BEGIN (61) */
 /* USER CODE END */
 
     adc1ParityCheck();
-
+    
 /* USER CODE BEGIN (62) */
 /* USER CODE END */
 
     adc2ParityCheck();
-
+    
 /* USER CODE BEGIN (63) */
 /* USER CODE END */
 
     can1ParityCheck();
-
+    
 /* USER CODE BEGIN (64) */
 /* USER CODE END */
 
     can2ParityCheck();
-
+    
 /* USER CODE BEGIN (65) */
 /* USER CODE END */
 
     can3ParityCheck();
-
+    
 /* USER CODE BEGIN (66) */
 /* USER CODE END */
 
     vimParityCheck();
-
+    
 /* USER CODE BEGIN (67) */
 /* USER CODE END */
 
@@ -602,45 +558,45 @@
 
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
-    {
-    }/* Wait */
+    { 
+    }/* Wait */                 
     /* wait for MibSPI1 RAM to complete initialization */
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
-    {
-    }/* Wait */
-    /* wait for MibSPI3 RAM to complete initialization */
+    { 
+    }/* Wait */                 
+    /* wait for MibSPI3 RAM to complete initialization */ 
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
-    {
-    }/* Wait */
+    { 
+    }/* Wait */                 
     /* wait for MibSPI5 RAM to complete initialization */
 
 /* USER CODE BEGIN (69) */
 /* USER CODE END */
 
     mibspi1ParityCheck();
-
+    
 /* USER CODE BEGIN (70) */
 /* USER CODE END */
 
     mibspi3ParityCheck();
-
+    
 /* USER CODE BEGIN (71) */
 /* USER CODE END */
-
+    
     mibspi5ParityCheck();
+    
 
-
 /* USER CODE BEGIN (72) */
 /* USER CODE END */
+    
 
-
 /* USER CODE BEGIN (73) */
 /* USER CODE END */
 
     /* Initialize VIM table */
-    vimInit();
+    vimInit();    
 
 /* USER CODE BEGIN (74) */
     // shuffle IRQ priorities per design requirements
@@ -661,7 +617,7 @@
     __TI_auto_init();
 /* USER CODE BEGIN (75) */
 /* USER CODE END */
-
+    
     /* call the application */
 /*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
 /*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
@@ -688,7 +644,7 @@
 /* USER CODE END */
 	while(1)
 	{
-
+		
 	}
 /* USER CODE BEGIN (80) */
 /* USER CODE END */