Index: firmware/App/DGCommon.h =================================================================== diff -u -rf43eb1e9e0803776ec7420b16e1db8760b020bd9 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/App/DGCommon.h (.../DGCommon.h) (revision f43eb1e9e0803776ec7420b16e1db8760b020bd9) +++ firmware/App/DGCommon.h (.../DGCommon.h) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -19,6 +19,12 @@ #include "hal_stdtypes.h" +// ********** version ********** + +#define DG_VERSION_MAJOR 0 +#define DG_VERSION_MINOR 3 +#define DG_VERSION_BUILD 0 + // ********** build switches ********** #ifndef _VECTORCAST_ Index: firmware/App/Services/AlarmMgmt.h =================================================================== diff -u -rb64c49fdcf2b6d95e61e63f8e258c4e600935bbd -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/App/Services/AlarmMgmt.h (.../AlarmMgmt.h) (revision b64c49fdcf2b6d95e61e63f8e258c4e600935bbd) +++ firmware/App/Services/AlarmMgmt.h (.../AlarmMgmt.h) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -122,6 +122,8 @@ SW_FAULT_ID_MSG_PENDING_ACK_LIST_FULL, SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER, SW_FAULT_ID_PI_CTRL_INVALID_SIGNAL, + SW_FAULT_ID_NVDATAMGMT_EXEC_INVALID_STATE, + SW_FAULT_ID_NVDATAMGMT_INVALID_SELF_TEST_STATE, NUM_OF_SW_FAULT_IDS } SW_FAULT_ID_T; Index: firmware/App/Services/SystemComm.c =================================================================== diff -u -r8b56b0c617ac49536b8d53852b9621be873bade6 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/App/Services/SystemComm.c (.../SystemComm.c) (revision 8b56b0c617ac49536b8d53852b9621be873bade6) +++ firmware/App/Services/SystemComm.c (.../SystemComm.c) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -790,10 +790,8 @@ { sendACKMsg( &message.msg ); } - else - { // otherwise, process the received message - processReceivedMessage( &message.msg ); - } + // otherwise, process the received message + processReceivedMessage( &message.msg ); } } else // CRC failed Index: firmware/DG.dil =================================================================== diff -u -ra49bd0780d97bb4ce04a9d7b128a6e3c2df044e1 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/DG.dil (.../DG.dil) (revision a49bd0780d97bb4ce04a9d7b128a6e3c2df044e1) +++ firmware/DG.dil (.../DG.dil) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -1,4 +1,4 @@ -# RM46L852PGE 03/23/20 11:42:59 +# RM46L852PGE 04/02/20 08:58:55 # ARCH=RM46L852PGE # @@ -119,7 +119,7 @@ DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0600 @@ -475,7 +475,7 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xf07fffff DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0 @@ -1569,7 +1569,7 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT5_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULDIS.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=0 @@ -1579,7 +1579,7 @@ DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_PDR.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULL.VALUE=2 DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT3_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT4_PULL.VALUE=1 @@ -1590,7 +1590,7 @@ DRIVER.GIO.VAR.GIO_PORT1_BIT1_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_POL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT4_ENA.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT0_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT0_PSL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT4_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT4_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_BASE_PORTA.VALUE=0xFFF7BC34 @@ -9348,12 +9348,12 @@ DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=6888 DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=66666.667 DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 @@ -9369,7 +9369,7 @@ DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 @@ -9380,25 +9380,25 @@ DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=6888 DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=66667 DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL -DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=996.758 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 @@ -9413,7 +9413,7 @@ DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=503.218 @@ -9469,7 +9469,7 @@ DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=996.758 DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 @@ -9481,7 +9481,7 @@ DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000 @@ -9503,7 +9503,7 @@ DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL -DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=66666.667 DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=0.000 @@ -9545,7 +9545,7 @@ DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=77.418 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=66666.667 DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 @@ -9562,7 +9562,7 @@ DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=77.418 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=66667 DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=0 @@ -9583,7 +9583,7 @@ DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=503.218 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 @@ -9644,7 +9644,7 @@ DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=996.758 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 @@ -9655,7 +9655,7 @@ DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 @@ -9679,12 +9679,12 @@ DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=996.758 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT -DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=0 @@ -9701,7 +9701,7 @@ DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=66667 DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 @@ -9710,7 +9710,7 @@ DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=66666.667 DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 @@ -9731,7 +9731,7 @@ DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED -DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 @@ -9786,10 +9786,10 @@ DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=996.758 DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 @@ -9799,7 +9799,7 @@ DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=6888 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 @@ -9847,7 +9847,7 @@ DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=52 DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=6888 DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 @@ -9870,7 +9870,7 @@ DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=66667 DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 Index: firmware/include/etpwm.h =================================================================== diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/include/etpwm.h (.../etpwm.h) (revision 6d2d8f0267c57135554e5a1acaca9aef37f27949) +++ firmware/include/etpwm.h (.../etpwm.h) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -468,13 +468,13 @@ #define ETPWM1_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM1_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM1_TBPRD_CONFIGVALUE 25833U +#define ETPWM1_TBPRD_CONFIGVALUE 6888U #define ETPWM1_CMPCTL_CONFIGVALUE 0x00000000U #define ETPWM1_CMPA_CONFIGVALUE 0U #define ETPWM1_CMPB_CONFIGVALUE 0U #define ETPWM1_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM1_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM1_DBRED_CONFIGVALUE 1U #define ETPWM1_DBFED_CONFIGVALUE 1U #define ETPWM1_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -520,13 +520,13 @@ #define ETPWM3_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM3_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM3_TBPRD_CONFIGVALUE 25833U +#define ETPWM3_TBPRD_CONFIGVALUE 6888U #define ETPWM3_CMPCTL_CONFIGVALUE 0x00000000U #define ETPWM3_CMPA_CONFIGVALUE 0U #define ETPWM3_CMPB_CONFIGVALUE 0U #define ETPWM3_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM3_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM3_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM3_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM3_DBRED_CONFIGVALUE 1U #define ETPWM3_DBFED_CONFIGVALUE 1U #define ETPWM3_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -546,7 +546,7 @@ #define ETPWM4_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM4_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM4_TBPRD_CONFIGVALUE 25833U +#define ETPWM4_TBPRD_CONFIGVALUE 102U #define ETPWM4_CMPCTL_CONFIGVALUE 0x00000000U #define ETPWM4_CMPA_CONFIGVALUE 0U #define ETPWM4_CMPB_CONFIGVALUE 0U @@ -604,7 +604,7 @@ #define ETPWM6_CMPB_CONFIGVALUE 0U #define ETPWM6_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM6_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM6_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM6_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM6_DBRED_CONFIGVALUE 1U #define ETPWM6_DBFED_CONFIGVALUE 1U #define ETPWM6_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -624,7 +624,7 @@ #define ETPWM7_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM7_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM7_TBPRD_CONFIGVALUE 25833U +#define ETPWM7_TBPRD_CONFIGVALUE 102U #define ETPWM7_CMPCTL_CONFIGVALUE 0x00000000U #define ETPWM7_CMPA_CONFIGVALUE 0U #define ETPWM7_CMPB_CONFIGVALUE 0U Index: firmware/include/gio.h =================================================================== diff -u -r0774a37971585dacdc8398362393920c13d48426 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/include/gio.h (.../gio.h) (revision 0774a37971585dacdc8398362393920c13d48426) +++ firmware/include/gio.h (.../gio.h) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -128,9 +128,9 @@ #define GIO_PORTAPSL_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 7U)) #define GIO_PORTAPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U)) -#define GIO_PORTBDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTBDIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTBPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) -#define GIO_PORTBPSL_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTBPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTBPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) Index: firmware/source/etpwm.c =================================================================== diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/source/etpwm.c (.../etpwm.c) (revision 6d2d8f0267c57135554e5a1acaca9aef37f27949) +++ firmware/source/etpwm.c (.../etpwm.c) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -82,7 +82,7 @@ etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG1->TBPRD = 25833U; + etpwmREG1->TBPRD = 6888U; /** - Setup the duty cycle for PWMA */ etpwmREG1->CMPA = 0U; @@ -107,7 +107,7 @@ | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -272,7 +272,7 @@ etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG3->TBPRD = 25833U; + etpwmREG3->TBPRD = 6888U; /** - Setup the duty cycle for PWMA */ etpwmREG3->CMPA = 0U; @@ -297,7 +297,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -359,101 +359,6 @@ etpwmREG3->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM4 */ - - /** - Sets high speed time-base clock prescale bits */ - etpwmREG4->TBCTL = (uint16)0U << 7U; - - /** - Sets time-base clock prescale bits */ - etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG4->TBPRD = 25833U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG4->CMPA = 0U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG4->CMPB = 0U; - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG4->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG4->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG4->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG4->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - /** - Set trip source enable */ - etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG4->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG4->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG4->ETSEL & 0x0007U) != 0U) - { - etpwmREG4->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG4->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG4->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM6 */ /** - Sets high speed time-base clock prescale bits */ @@ -489,7 +394,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -552,104 +457,8 @@ etpwmREG6->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM7 */ - /** - Sets high speed time-base clock prescale bits */ - etpwmREG7->TBCTL = (uint16)0U << 7U; - /** - Sets time-base clock prescale bits */ - etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG7->TBPRD = 25833U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG7->CMPA = 0U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG7->CMPB = 0U; - - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG7->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG7->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG7->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG7->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG7->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - - /** - Set trip source enable */ - etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG7->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG7->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG7->ETSEL & 0x0007U) != 0U) - { - etpwmREG7->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG7->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG7->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG7->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - - /* USER CODE BEGIN (2) */ /* USER CODE END */ } Index: firmware/source/gio.c =================================================================== diff -u -r0774a37971585dacdc8398362393920c13d48426 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/source/gio.c (.../gio.c) (revision 0774a37971585dacdc8398362393920c13d48426) +++ firmware/source/gio.c (.../gio.c) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -133,7 +133,7 @@ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port B direction */ - gioPORTB->DIR = (uint32)((uint32)1U << 0U) /* Bit 0 */ + gioPORTB->DIR = (uint32)((uint32)0U << 0U) /* Bit 0 */ | (uint32)((uint32)1U << 1U) /* Bit 1 */ | (uint32)((uint32)0U << 2U) /* Bit 2 */ | (uint32)((uint32)0U << 3U) /* Bit 3 */ @@ -153,7 +153,7 @@ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port B pullup / pulldown selection */ - gioPORTB->PSL = (uint32)((uint32)0U << 0U) /* Bit 0 */ + gioPORTB->PSL = (uint32)((uint32)1U << 0U) /* Bit 0 */ | (uint32)((uint32)0U << 1U) /* Bit 1 */ | (uint32)((uint32)1U << 2U) /* Bit 2 */ | (uint32)((uint32)0U << 3U) /* Bit 3 */ Index: firmware/source/sys_main.c =================================================================== diff -u -rf267c42c91fd6e22db80e19039b8993582de51e9 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/source/sys_main.c (.../sys_main.c) (revision f267c42c91fd6e22db80e19039b8993582de51e9) +++ firmware/source/sys_main.c (.../sys_main.c) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -131,11 +131,11 @@ mibspiInit(); // configure MIBSPI3 and re-purpose MIBSPI1 & 5 pins for GPIO etpwmInit(); // configure PWMs etpwmSetCmpA( etpwmREG1, 0 ); - etpwmSetCmpA( etpwmREG2, 0 ); + etpwmSetCmpB( etpwmREG1, 0 ); + etpwmSetCmpB( etpwmREG2, 0 ); etpwmSetCmpA( etpwmREG3, 0 ); - etpwmSetCmpA( etpwmREG4, 0 ); etpwmSetCmpA( etpwmREG6, 0 ); - etpwmSetCmpA( etpwmREG7, 0 ); + etpwmSetCmpB( etpwmREG6, 0 ); canInit(); // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO sciInit(); // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface dmaEnable(); // enable DMA