Index: firmware/source/crc.c =================================================================== diff -u --- firmware/source/crc.c (revision 0) +++ firmware/source/crc.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,552 @@ +/** @file crc.c +* @brief CRC Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the CRC driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "crc.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void crcInit(void) +* @brief Initializes the crc Driver +* +* This function initializes the crc module. +*/ +/* SourceId : CRC_SourceId_001 */ +/* DesignId : CRC_DesignId_001 */ +/* Requirements: HL_SR107 */ +void crcInit(void) +{ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + /** @b initialize @b CRC */ + + /** - Reset PSA*/ + crcREG->CTRL0 = (uint32)((uint32)1U << 0U) + | (uint32)((uint32)1U << 8U); + + /** - Pulling PSA out of reset */ + crcREG->CTRL0=0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG->CTRL2 |= (uint32)0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG->INTS= 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U + | 0x00000000U; + + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG->PCOUNT_REG1=0x00000000U; + crcREG->PCOUNT_REG2=0x00000000U; + + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG->SCOUNT_REG1=0x00000000U; + crcREG->SCOUNT_REG2=0x00000000U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG->WDTOPLD1=0x00000000U; + crcREG->WDTOPLD2=0x00000000U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG->BCTOPLD1=0x00000000U; + crcREG->BCTOPLD2=0x00000000U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG->REGL1=0x00000000U; + crcREG->REGL2=0x00000000U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG->REGH1=0x00000000U; + crcREG->REGH2=0x00000000U; + + /** - Setup the Channel mode */ + crcREG->CTRL2 |= (uint32)(CRC_FULL_CPU) | (uint32)((uint32)CRC_FULL_CPU << 8U); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +} + + +/** @fn void crcSendPowerDown(crcBASE_t *crc) +* @brief Send crc power down +* @param[in] crc - crc module base address +* +* Send crc power down signal to enter into sleep mode +*/ +/* SourceId : CRC_SourceId_002 */ +/* DesignId : CRC_DesignId_002 */ +/* Requirements: HL_SR108 */ +void crcSendPowerDown(crcBASE_t *crc) +{ +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + crc->CTRL1 |= 0x00000001U; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ +} + +/** @fn void crcSignGen(crcBASE_t *crc,crcModConfig_t *param) +* @brief set the mode specific parameters for signature generation +* @param[in] crc - crc module base address +* @param[in] param - structure holding mode specific parameters +* Generate CRC signature +*/ +/* SourceId : CRC_SourceId_003 */ +/* DesignId : CRC_DesignId_003 */ +/* Requirements: HL_SR109 */ +void crcSignGen(crcBASE_t *crc,crcModConfig_t *param) +{ +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + uint32 i = 0U, psaSigx; + volatile uint64 * ptr64, * psaSigx_ptr64; + ptr64=param->src_data_pat; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 439 S MR:11.3 "Pointer Manupulation required to find offset - Advisory as per MISRA" */ + psaSigx = (uint32)(&crc->PSA_SIGREGL1) + ((uint32)(param->crc_channel) * 0x40U); + psaSigx_ptr64 = (uint64 *) (psaSigx); + + if(param->mode==CRC_AUTO) + { +/** -do a channel reset +* -clear all interrupts by reading offset register +* -set CRC FAIL interrupt +* -set the pattern count and sector count +* -HW trigger in AUTO mode for CRC register update +* -copy from memory location to CRC register using DMA +* -copy from memory to PSA signature register using DMA +* -frame or block transfer,auto init +* -compare with crc reference +* -do a channel reset +*/ + } + else if(param->mode==CRC_SEMI_CPU) + { + /* after DMA does the transfer,CPU is invoked by CC interrupt to do signature verification */ + } + else if(param->mode==CRC_FULL_CPU) + { + for(i=0U;idata_length;i++) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + *psaSigx_ptr64 = *ptr64; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr64++; + } +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + } + else + { + /* Empty */ + } +} + +/** @fn void crcSetConfig(crcBASE_t *crc,crcConfig_t *param) +* @brief Set crc configurations +* @param[in] crc - crc module base address +* @param[in] param - structure for channel configuration +* Set Channel parameters +*/ +/* SourceId : CRC_SourceId_004 */ +/* DesignId : CRC_DesignId_004 */ +/* Requirements: HL_SR110 */ +void crcSetConfig(crcBASE_t *crc,crcConfig_t *param) +{ +/* USER CODE BEGIN (8) */ +/* USER CODE END */ + + switch (param->crc_channel) + { + case 0U: + crc->CTRL2 &=0xFFFFFFFCU; + crc->CTRL0 |=0x00000001U; + crc->CTRL0 &=0xFFFFFFFEU; + crc->PCOUNT_REG1 = param->pcount; + crc->SCOUNT_REG1 = param->scount; + crc->WDTOPLD1= param->wdg_preload; + crc->BCTOPLD1= param->block_preload; + crc->CTRL2 |= param->mode; + break; + case 1U: + crc->CTRL2 &=0xFFFFFCFFU; + crc->CTRL0 |=0x00000100U; + crc->CTRL0 &=0xFFFFFEFFU; + crc->PCOUNT_REG2 = param->pcount; + crc->SCOUNT_REG2= param->scount; + crc->WDTOPLD2= param->wdg_preload; + crc->BCTOPLD2= param->block_preload; + crc->CTRL2 |= (uint32)((uint32)param->mode << 8U); + break; + default : + break; + } + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ +} + +/** @fn uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel) +* @brief get generated sector signature +* @param[in] crc - crc module base address +* @param[in] channel - crc channel +* CRC_CH1 - channel1 +* CRC_CH2 - channel2 +* CRC_CH3 - channel3 +* CRC_CH4 - channel4 +* +* Get Sector signature value of selected channel +*/ +/* SourceId : CRC_SourceId_005 */ +/* DesignId : CRC_DesignId_006 */ +/* Requirements: HL_SR111 */ +uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel) +{ + uint64 status=0U; + uint32 CRC_PSA_SECSIGREGH1 = crcREG->PSA_SECSIGREGH1; + uint32 CRC_PSA_SECSIGREGL1 = crcREG->PSA_SECSIGREGL1; + uint32 CRC_PSA_SECSIGREGH2 = crcREG->PSA_SECSIGREGH2; + uint32 CRC_PSA_SECSIGREGL2 = crcREG->PSA_SECSIGREGL2; + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + switch (channel) + { + case 0U: + status = (((uint64)(CRC_PSA_SECSIGREGL1) << 32U) | (uint64)(CRC_PSA_SECSIGREGH1)); + break; + case 1U: + status = (((uint64)(CRC_PSA_SECSIGREGL2) << 32U) | (uint64)(CRC_PSA_SECSIGREGH2)); + break; + default : + break; + } + return status; + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +} + + +/** @fn uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel) +* @brief get failed sector details +* @param[in] crc - crc module base address +* @param[in] channel - crc channel +* CRC_CH1 - channel1 +* CRC_CH2 - channel2 +* CRC_CH3 - channel3 +* CRC_CH4 - channel4 +* +* Get Failed Sector value of selected channel +*/ +/* SourceId : CRC_SourceId_006 */ +/* DesignId : CRC_DesignId_007 */ +/* Requirements: HL_SR112 */ +uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel) +{ + + uint32 sector=0U; + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + + switch (channel) + { + case 0U: + sector = crc->CURSEC_REG1; + break; + case 1U: + sector = crc->CURSEC_REG2; + break; + default : + break; + } + return sector; +/* USER CODE BEGIN (13) */ +/* USER CODE END */ +} + +/** @fn uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel) +* @brief get highest priority interrupt pending +* @param[in] crc - crc module base address +* @param[in] channel - crc channel +* +* Get pending Interrupts of selected channel +*/ +/* SourceId : CRC_SourceId_007 */ +/* DesignId : CRC_DesignId_008 */ +/* Requirements: HL_SR113 */ +uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel) +{ +/* USER CODE BEGIN (14) */ +/* USER CODE END */ + return crc->INT_OFFSET_REG; +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +} + + +/** @fn void crcChannelReset(crcBASE_t *crc,uint32 channel) +* @brief Reset the channel configurations +* @param[in] crc - crc module base address +* @param[in] channel-crc channel +* CRC_CH1 - channel1 +* CRC_CH2 - channel2 +* CRC_CH3 - channel3 +* CRC_CH4 - channel4 +* +* Reset configurations of the selected channels. +*/ +/* SourceId : CRC_SourceId_008 */ +/* DesignId : CRC_DesignId_009 */ +/* Requirements: HL_SR114 */ +void crcChannelReset(crcBASE_t *crc,uint32 channel) +{ +/* USER CODE BEGIN (16) */ +/* USER CODE END */ + + if(channel == 0U) + { + crc->CTRL0 |= (uint32)((uint32)1U << 0U); /** Reset the CRC channel */ + crc->CTRL0 &= ~(uint32)((uint32)1U << 0U); /** Exit the reset */ + } + else if(channel == 1U) + { + crc->CTRL0 |= (uint32)((uint32)1U << 8U); /** Reset the CRC channel */ + crc->CTRL0 &= ~(uint32)((uint32)1U << 8U); /** Exit the reset */ + } + else + { + /** Empty */ + } +/* USER CODE BEGIN (17) */ +/* USER CODE END */ + } + + +/** @fn crcEnableNotification(crcBASE_t *crc, uint32 flags) +* @brief Enable interrupts +* @param[in] crc - crc module base address +* @param[in] flags - Interrupts to be enabled, can be ored value of: +* CRC_CH2_TO - channel3 timeout error, +* CRC_CH2_UR - channel3 underrun error, +* CRC_CH2_OR - channel3 overrun error, +* CRC_CH2_FAIL - channel3 crc error, +* CRC_CH2_CC - channel3 compression complete interrupt , +* CRC_CH1_TO - channel4 timeout error, +* CRC_CH1_UR - channel4 underrun error, +* CRC_CH1_OR - channel4 overrun error, +* CRC_CH1_FAIL - channel4 crc error, +* CRC_CH1_CC - channel4 compression complete interrupt +* +* Enable Notifications / Interrupts +*/ +/* SourceId : CRC_SourceId_009 */ +/* DesignId : CRC_DesignId_010 */ +/* Requirements: HL_SR115 */ +void crcEnableNotification(crcBASE_t *crc, uint32 flags) +{ +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + + crc->INTS= flags; + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +} + + +/** @fn crcDisableNotification(crcBASE_t *crc, uint32 flags) +* @brief Disable interrupts +* @param[in] crc - crc module base address +* @param[in] flags - Interrupts to be disabled, can be ored value of: +* CRC_CH2_TO - channel3 timeout error, +* CRC_CH2_UR - channel3 underrun error, +* CRC_CH2_OR - channel3 overrun error, +* CRC_CH2_FAIL - channel3 crc error, +* CRC_CH2_CC - channel3 compression complete interrupt , +* CRC_CH1_TO - channel4 timeout error, +* CRC_CH1_UR - channel4 underrun error, +* CRC_CH1_OR - channel4 overrun error, +* CRC_CH1_FAIL - channel4 crc error, +* CRC_CH1_CC - channel4 compression complete interrupt +* +* Disable Notifications / Interrupts +*/ +/* SourceId : CRC_SourceId_010 */ +/* DesignId : CRC_DesignId_011 */ +/* Requirements: HL_SR116 */ +void crcDisableNotification(crcBASE_t *crc, uint32 flags) +{ +/* USER CODE BEGIN (20) */ +/* USER CODE END */ + + crc->INTR= flags; + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +} + +/** @fn uint32 crcGetPSASig(crcBASE_t *crc,uint32 channel) +* @brief get genearted PSA signature used for FULL CPU mode +* @param[in] crc - crc module base address +* @param[in] channel - crc channel +* CRC_CH1 - channel1 +* CRC_CH2 - channel2 +* CRC_CH3 - channel3 +* CRC_CH4 - channel4 +* +* Get PSA signature used for FULL CPU mode of selected channel +*/ +/* SourceId : CRC_SourceId_011 */ +/* DesignId : CRC_DesignId_005 */ +/* Requirements: HL_SR525 */ +uint64 crcGetPSASig(crcBASE_t *crc,uint32 channel) +{ + uint64 status = 0U; + uint32 CRC_PSA_SIGREGH1 = crcREG->PSA_SIGREGH1; + uint32 CRC_PSA_SIGREGL1 = crcREG->PSA_SIGREGL1; + uint32 CRC_PSA_SIGREGH2 = crcREG->PSA_SIGREGH2; + uint32 CRC_PSA_SIGREGL2 = crcREG->PSA_SIGREGL2; + +/* USER CODE BEGIN (22) */ +/* USER CODE END */ + switch (channel) + { + case 0U: + status = (((uint64)(CRC_PSA_SIGREGL1) << 32U) | (uint64)(CRC_PSA_SIGREGH1)); + break; + case 1U: + status = (((uint64)(CRC_PSA_SIGREGL2) << 32U) | (uint64)(CRC_PSA_SIGREGH2)); + break; + default : + break; + } + return status; + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ +} + + +/** @fn void crcGetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the CRC configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : CRC_SourceId_012 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements: HL_SR119 */ +void crcGetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRL0 = CRC_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_CTRL0 = crcREG->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG->CTRL2; + config_reg->CONFIG_INTS = crcREG->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG->BCTOPLD2; + } +} + + Index: firmware/source/ecap.c =================================================================== diff -u --- firmware/source/ecap.c (revision 0) +++ firmware/source/ecap.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,976 @@ +/** @file ecap.c +* @brief ECAP Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the ECAP driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "ecap.h" +#include "sys_vim.h" + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void ecapInit(void) +* @brief Initializes the eCAP Driver +* +* This function initializes the eCAP module. +*/ +/* SourceId : ECAP_SourceId_001 */ +/* DesignId : ECAP_DesignId_001 */ +/* Requirements : HL_ECAP_SR1 */ +void ecapInit(void) +{ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /** @b initialize @b ECAP1 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG1->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG1->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG1->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP2 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG2->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG2->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG2->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP3 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG3->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG3->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG3->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP4 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG4->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG4->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG4->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP5 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG5->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG5->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG5->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP6 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG6->ECCTL1 = ((uint16)((uint16)RISING_EDGE << 0U) /* Capture Event 1 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 1U) /* Counter Reset on Capture Event 1 */ + | (uint16)((uint16)RISING_EDGE << 2U) /* Capture Event 2 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 3U) /* Counter Reset on Capture Event 2 */ + | (uint16)((uint16)RISING_EDGE << 4U) /* Capture Event 3 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 5U) /* Counter Reset on Capture Event 3 */ + | (uint16)((uint16)RISING_EDGE << 6U) /* Capture Event 4 Polarity */ + | (uint16)((uint16)RESET_DISABLE << 7U) /* Counter Reset on Capture Event 4 */ + | (uint16)((uint16)0U << 8U) /* Enable/Disable loading on a capture event */ + | (uint16)((uint16)0U << 9U)); /* Setup Event Filter prescale */ + + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG6->ECCTL2 = (uint16)((uint16)ONE_SHOT << 0U) /* Capture Mode */ + | (uint16)((uint16)CAPTURE_EVENT1 << 1U) /* Stop/Wrap value */ + | (uint16)((uint16)0U << 9U) /* Enable/Disable APWM mode */ + | (uint16)0x00000010U; /* Start counter */ + + + + /** - Set interrupt enable */ + ecapREG6->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + +} + +/** @fn void ecapSetCounter(ecapBASE_t *ecap, uint32 value) +* @brief Set Time-Stamp Counter +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] value 16-bit Counter value +* +* This function sets the Time-Stamp Counter register +*/ +/* SourceId : ECAP_SourceId_002 */ +/* DesignId : ECAP_DesignId_002 */ +/* Requirements : HL_ECAP_SR2 */ +void ecapSetCounter(ecapBASE_t *ecap, uint32 value) +{ + ecap->TSCTR = value; +} + +/** @fn void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase) +* @brief Enable counter register load from phase register when a sync event occurs +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] phase Counter value to be loaded when a sync event occurs +* +* This function enables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ECAP_SourceId_003 */ +/* DesignId : ECAP_DesignId_003 */ +/* Requirements : HL_ECAP_SR3 */ +void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase) +{ + ecap->ECCTL2 |= 0x0020U; + ecap->CTRPHS = phase; +} + +/** @fn void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap) +* @brief Disable counter register load from phase register when a sync event occurs +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function disables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ECAP_SourceId_004 */ +/* DesignId : ECAP_DesignId_004 */ +/* Requirements : HL_ECAP_SR3 */ +void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap) +{ + ecap->ECCTL2 &= (uint16)~(uint16)0x0020U; +} + +/** @fn void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale) +* @brief Set Event prescaler +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] prescale Event Filter prescale select (ecapPrescale_By_1..ecapPrescale_By_62) +* +* This function disables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ECAP_SourceId_005 */ +/* DesignId : ECAP_DesignId_005 */ +/* Requirements : HL_ECAP_SR4 */ +void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale) +{ + ecap->ECCTL1 &= (uint16)~(uint16)0x3E00U; + ecap->ECCTL1 |= (uint16)prescale; +} + +/** @fn void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +* @brief Set Capture Event 1 +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] edgePolarity Capture Event 1 Polarity select +* - RISING_EDGE +* - FALLING_EDGE +* @param[in] resetenable Counter Reset on Capture Event 1 +* - RESET_ENABLE +* - RESET_DISABLE +* +* This function sets the polarity and reset enable for Capture event 1 +*/ +/* SourceId : ECAP_SourceId_006 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : HL_ECAP_SR5 */ +void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +{ + ecap->ECCTL1 &= (uint16)~(uint16)((uint16)0x3U << 0U); + ecap->ECCTL1 |= (uint16)(((uint16)edgePolarity | (uint16)((uint16)resetenable << 1U)) << 0U); +} + +/** @fn void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +* @brief Set Capture Event 2 +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] edgePolarity Capture Event 2 Polarity select +* - RISING_EDGE +* - FALLING_EDGE +* @param[in] resetenable Counter Reset on Capture Event 2 +* - RESET_ENABLE +* - RESET_DISABLE +* +* This function sets the polarity and reset enable for Capture event 2 +*/ +/* SourceId : ECAP_SourceId_007 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : HL_ECAP_SR5 */ +void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +{ + ecap->ECCTL1 &= (uint16)~(uint16)((uint16)0x3U << 2U); + ecap->ECCTL1 |= (uint16)(((uint16)edgePolarity | (uint16)((uint16)resetenable << 1U)) << 2U); +} + +/** @fn void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +* @brief Set Capture Event 3 +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] edgePolarity Capture Event 3 Polarity select +* - RISING_EDGE +* - FALLING_EDGE +* @param[in] resetenable Counter Reset on Capture Event 3 +* - RESET_ENABLE +* - RESET_DISABLE +* +* This function sets the polarity and reset enable for Capture event 3 +*/ +/* SourceId : ECAP_SourceId_008 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : HL_ECAP_SR5 */ +void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +{ + ecap->ECCTL1 &= (uint16)~(uint16)((uint16)0x3U << 4U); + ecap->ECCTL1 |= (uint16)(((uint16)edgePolarity | (uint16)((uint16)resetenable << 1U)) << 4U); +} + +/** @fn void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +* @brief Set Capture Event 4 +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] edgePolarity Capture Event 4 Polarity select +* - RISING_EDGE +* - FALLING_EDGE +* @param[in] resetenable Counter Reset on Capture Event 4 +* - RESET_ENABLE +* - RESET_DISABLE +* +* This function sets the polarity and reset enable for Capture event 4 +*/ +/* SourceId : ECAP_SourceId_009 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : HL_ECAP_SR1 */ +void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, ecapReset_t resetenable) +{ + ecap->ECCTL1 &= (uint16)~(uint16)((uint16)0x3U << 6U); + ecap->ECCTL1 |= (uint16)(((uint16)edgePolarity | (uint16)((uint16)resetenable << 1U)) << 6U); +} + +/** @fn void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t mode, ecapEvent_t event) +* @brief Set Capture mode +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] capMode Capture mode +* - CONTINUOUS +* - ONE_SHOT +* @param[in] event Stop/Wrap value +* - CAPTURE_EVENT1: Stop after Capture Event 1 in one-shot mode / Wrap after Capture Event 1 in continuous mode +* - CAPTURE_EVENT2: Stop after Capture Event 2 in one-shot mode / Wrap after Capture Event 2 in continuous mode. +* - CAPTURE_EVENT3: Stop after Capture Event 3 in one-shot mode / Wrap after Capture Event 3 in continuous mode. +* - CAPTURE_EVENT4: Stop after Capture Event 4 in one-shot mode / Wrap after Capture Event 4 in continuous mode. +* +* This function sets the capture mode and stop/wrap value +*/ +/* SourceId : ECAP_SourceId_010 */ +/* DesignId : ECAP_DesignId_007 */ +/* Requirements : HL_ECAP_SR6 */ +void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t capMode, ecapEvent_t event) +{ + ecap->ECCTL2 &= 0xFFF8U; + ecap->ECCTL2 |= ((uint16)((uint16)event << 1U) | (uint16)capMode); +} + +/** @fn void ecapEnableCapture(ecapBASE_t *ecap) +* @brief Enable Capture +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function enable loading of CAP1-4 registers on a capture event +*/ +/* SourceId : ECAP_SourceId_011 */ +/* DesignId : ECAP_DesignId_008 */ +/* Requirements : HL_ECAP_SR7 */ +void ecapEnableCapture(ecapBASE_t *ecap) +{ + ecap->ECCTL1 |= 0x0100U; +} + +/** @fn void ecapDisableCapture(ecapBASE_t *ecap) +* @brief Disable Capture +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function disable loading of CAP1-4 registers on a capture event +*/ +/* SourceId : ECAP_SourceId_012 */ +/* DesignId : ECAP_DesignId_009 */ +/* Requirements : HL_ECAP_SR7 */ +void ecapDisableCapture(ecapBASE_t *ecap) +{ + ecap->ECCTL1 &= (uint16)~(uint16)0x0100U; +} + +/** @fn void ecapStartCounter(ecapBASE_t *ecap) +* @brief Start Time Stamp Counter +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function starts Time Stamp Counter +*/ +/* SourceId : ECAP_SourceId_013 */ +/* DesignId : ECAP_DesignId_010 */ +/* Requirements : HL_ECAP_SR8 */ +void ecapStartCounter(ecapBASE_t *ecap) +{ + ecap->ECCTL2 |= 0x0010U; +} + +/** @fn void ecapStopCounter(ecapBASE_t *ecap)) +* @brief Stop Time Stamp Counter +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function stops Time Stamp Counter +*/ +/* SourceId : ECAP_SourceId_014 */ +/* DesignId : ECAP_DesignId_011 */ +/* Requirements : HL_ECAP_SR8 */ +void ecapStopCounter(ecapBASE_t *ecap) +{ + ecap->ECCTL2 &= (uint16)~(uint16)0x0010U; +} + +/** @fn void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc) +* @brief Set the source of Sync-out signal +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] syncOutSrc Sync-Out Select +* - SyncOut_SyncIn: Sync In used for Sync Out +* - SyncOut_CTRPRD: CTR = PRD used for Sync Out +* - SyncOut_None : Disables Sync Out +* +* This function sets the source of Sync-out signal +*/ +/* SourceId : ECAP_SourceId_015 */ +/* DesignId : ECAP_DesignId_012 */ +/* Requirements : HL_ECAP_SR9 */ +void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc) +{ + ecap->ECCTL2 &= (uint16)~(uint16)0x00C0U; + ecap->ECCTL2 |= syncOutSrc; +} + +/** @fn void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint16 period, uint16 duty) +* @brief Enable APWM mode +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] pwmPolarity APWM output polarity select +* - ACTIVE_HIGH +* - ACTIVE_LOW +* @param[in] period APWM period (in terms of ticks) +* @param[in] duty APWM duty (in terms of ticks) +* +* This function enables and sets APWM mode +*/ +/* SourceId : ECAP_SourceId_016 */ +/* DesignId : ECAP_DesignId_013 */ +/* Requirements : HL_ECAP_SR10 */ +void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint32 period, uint32 duty) +{ + ecap->ECCTL2 &= (uint16)~(uint16)0x0400U; + ecap->ECCTL2 |= (uint16)((uint16)pwmPolarity << 10U) | (uint16)((uint16)1U << 9U); + ecap->CAP1 = period - 1U; + ecap->CAP2 = duty; +} + +/** @fn void ecapDisableAPWMMode(ecapBASE_t *ecap) +* @brief Disable APWM mode +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function disables APWM mode +*/ +/* SourceId : ECAP_SourceId_017 */ +/* DesignId : ECAP_DesignId_014 */ +/* Requirements : HL_ECAP_SR10 */ +void ecapDisableAPWMMode(ecapBASE_t *ecap) +{ + ecap->ECCTL2 &= (uint16)~(uint16)0x0200U; +} + +/** @fn void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) +* @brief Enable eCAP interrupt sources +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] interrupts eCAP interrupt sources +* - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt +* - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt +* - ecapInt_CTR_OVF: Denotes CTROVF interrupt +* - ecapInt_CEVT4 : Denotes CEVT4 interrupt +* - ecapInt_CEVT3 : Denotes CEVT3 interrupt +* - ecapInt_CEVT2 : Denotes CEVT2 interrupt +* - ecapInt_CEVT1 : Denotes CEVT1 interrupt +* - ecapInt_All : Denotes All interrupts +* +* This function enables eCAP interrupt sources +*/ +/* SourceId : ECAP_SourceId_018 */ +/* DesignId : ECAP_DesignId_015 */ +/* Requirements : HL_ECAP_SR11 */ +void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) +{ + ecap->ECEINT |= interrupts; +} + +/** @fn void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) +* @brief Disables eCAP interrupt sources +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] interrupts eCAP interrupt sources +* - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt +* - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt +* - ecapInt_CTR_OVF: Denotes CTROVF interrupt +* - ecapInt_CEVT4 : Denotes CEVT4 interrupt +* - ecapInt_CEVT3 : Denotes CEVT3 interrupt +* - ecapInt_CEVT2 : Denotes CEVT2 interrupt +* - ecapInt_CEVT1 : Denotes CEVT1 interrupt +* - ecapInt_All : Denotes All interrupts +* +* This function disables eCAP interrupt sources +*/ +/* SourceId : ECAP_SourceId_019 */ +/* DesignId : ECAP_DesignId_016 */ +/* Requirements : HL_ECAP_SR11 */ +void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) +{ + ecap->ECEINT &= (uint16)~(uint16)interrupts; +} + +/** @fn uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events) +* @brief Return Event status +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] events eCAP events +* - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt +* - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt +* - ecapInt_CTR_OVF: Denotes CTROVF interrupt +* - ecapInt_CEVT4 : Denotes CEVT4 interrupt +* - ecapInt_CEVT3 : Denotes CEVT3 interrupt +* - ecapInt_CEVT2 : Denotes CEVT2 interrupt +* - ecapInt_CEVT1 : Denotes CEVT1 interrupt +* - ecapInt_Global : Denotes Capture global interrupt +* - ecapInt_All : Denotes All interrupts +* @return Event status +* +* This function returns the event status +*/ +/* SourceId : ECAP_SourceId_020 */ +/* DesignId : ECAP_DesignId_017 */ +/* Requirements : HL_ECAP_SR12 */ +uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events) +{ + return (ecap->ECFLG & events); +} + +/** @fn void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events) +* @brief Clear Event status +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* @param[in] events eCAP events +* - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt +* - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt +* - ecapInt_CTR_OVF: Denotes CTROVF interrupt +* - ecapInt_CEVT4 : Denotes CEVT4 interrupt +* - ecapInt_CEVT3 : Denotes CEVT3 interrupt +* - ecapInt_CEVT2 : Denotes CEVT2 interrupt +* - ecapInt_CEVT1 : Denotes CEVT1 interrupt +* - ecapInt_Global : Denotes Capture global interrupt +* - ecapInt_All : Denotes All interrupts +* +* This function clears the event status +*/ +/* SourceId : ECAP_SourceId_021 */ +/* DesignId : ECAP_DesignId_018 */ +/* Requirements : HL_ECAP_SR13 */ +void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events) +{ + ecap->ECCLR = events; +} + +/** @fn void uint32 ecapGetCAP1(ecapBASE_t *ecap) +* @brief Get CAP1 value +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function returns Capture 1 value +*/ +/* SourceId : ECAP_SourceId_022 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : HL_ECAP_SR14 */ +uint32 ecapGetCAP1(ecapBASE_t *ecap) +{ + return ecap->CAP1; +} + +/** @fn void uint32 ecapGetCAP2(ecapBASE_t *ecap) +* @brief Get CAP2 value +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function returns Capture 2 value +*/ +/* SourceId : ECAP_SourceId_023 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : HL_ECAP_SR14 */ +uint32 ecapGetCAP2(ecapBASE_t *ecap) +{ + return ecap->CAP2; +} + +/** @fn void uint32 ecapGetCAP3(ecapBASE_t *ecap) +* @brief Get CAP3 value +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function returns Capture 3 value +*/ +/* SourceId : ECAP_SourceId_024 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : HL_ECAP_SR14 */ +uint32 ecapGetCAP3(ecapBASE_t *ecap) +{ + return ecap->CAP3; +} + +/** @fn void uint32 ecapGetCAP4(ecapBASE_t *ecap) +* @brief Get CAP4 value +* +* @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) +* +* This function returns Capture 4 value +*/ +/* SourceId : ECAP_SourceId_025 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : HL_ECAP_SR14 */ +uint32 ecapGetCAP4(ecapBASE_t *ecap) +{ + return ecap->CAP4; +} + +/** @fn void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_026 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP1_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP1_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP1_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP1_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG1->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG1->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG1->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG1->ECEINT; + } +} + +/** @fn void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_027 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP2_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP2_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP2_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP2_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG2->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG2->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG2->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG2->ECEINT; + } +} + +/** @fn void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_028 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP3_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP3_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP3_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP3_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG3->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG3->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG3->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG3->ECEINT; + } +} + +/** @fn void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_029 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP4_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP4_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP4_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP4_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG4->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG4->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG4->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG4->ECEINT; + } +} + +/** @fn void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_030 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP5_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP5_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP5_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP5_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG5->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG5->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG5->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG5->ECEINT; + } +} + +/** @fn void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ECAP_SourceId_031 */ +/* DesignId : ECAP_DesignId_046 */ +/* Requirements : HL_ECAP_SR18 */ +void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_CTRPHS = ECAP6_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP6_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP6_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP6_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG6->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG6->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG6->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG6->ECEINT; + } +} + + + +/*end of file*/ Index: firmware/source/emac.c =================================================================== diff -u --- firmware/source/emac.c (revision 0) +++ firmware/source/emac.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,1745 @@ +/** + * \file emac.c + * + * \brief EMAC APIs. + * + * This file contains the device abstraction layer APIs for EMAC. + */ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emac.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Defining interface for all the emac instances */ +hdkif_t hdkif_data[MAX_EMAC_INSTANCE]; +/*SAFETYMCUSW 25 D MR:8.7 "Statically allocated memory needs to be available to entire application." */ +static uint8_t pbuf_array[MAX_RX_PBUF_ALLOC][MAX_TRANSFER_UNIT]; +/******************************************************************************* +* INTERNAL MACRO DEFINITIONS +*******************************************************************************/ +#define EMAC_CONTROL_RESET (0x01U) +#define EMAC_SOFT_RESET (0x01U) +#define EMAC_MAX_HEADER_DESC (8U) +#define EMAC_UNICAST_DISABLE (0xFFU) + +/******************************************************************************* +* API FUNCTION DEFINITIONS +*******************************************************************************/ +/** + * \brief Enables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC Control module + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_001 */ +/* DesignId : ETH_DesignId_001*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel) +{ + HWREG(emacBase + EMAC_TXINTMASKSET) |= ((uint32)1U << channel); + + HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) |= ((uint32)1U << channel); +} + +/** + * \brief Disables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC Control module + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_002 */ +/* DesignId : ETH_DesignId_002*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_TXINTMASKCLEAR) |= ((uint32)1U << channel); + + HWREG(emacCtrlBase + EMAC_CTRL_CnTXEN(ctrlCore)) &= (~((uint32)1U << channel)); +} + +/** + * \brief Enables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be enabled. + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_003 */ +/* DesignId : ETH_DesignId_003*/ +/* Requirements : HL_ETH_SR15 */ +void EMACRxIntPulseEnable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_RXINTMASKSET) |= ((uint32)1U << channel); + + HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) |= ((uint32)1U << channel); +} + +/** + * \brief Disables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be disabled. + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_004 */ +/* DesignId : ETH_DesignId_004*/ +/* Requirements : HL_ETH_SR15 */ +void EMACRxIntPulseDisable(uint32 emacBase, uint32 emacCtrlBase, uint32 ctrlCore, uint32 channel) +{ + HWREG(emacBase + EMAC_RXINTMASKCLEAR) |= ((uint32)1U << channel); + + HWREG(emacCtrlBase + EMAC_CTRL_CnRXEN(ctrlCore)) &= (~((uint32)1U << channel)); +} +/** + * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or + * 100 Mbps + * + * \param emacBase Base address of the EMAC Module registers. + * \param speed speed for setting. + * speed can take the following values. \n + * EMAC_RMIISPEED_10MBPS - 10 Mbps \n + * EMAC_RMIISPEED_100MBPS - 100 Mbps. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_005 */ +/* DesignId : ETH_DesignId_005*/ +/* Requirements : HL_ETH_SR19 */ +void EMACRMIISpeedSet(uint32 emacBase, uint32 speed) +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_RMIISPEED); + + HWREG(emacBase + EMAC_MACCONTROL) |= speed; +} +/* SourceId : ETH_SourceId_006 */ +/* DesignId : ETH_DesignId_006*/ +/* Requirements : HL_ETH_SR18 */ +/** + * \brief This API set the GMII bit, RX and TX are enabled for receive and transmit. + * Note: This is not the API to enable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +void EMACMIIEnable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_GMIIEN; +} + +/** + * \brief This API clears the GMII bit, Rx and Tx are held in reset. + * Note: This is not the API to disable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_007 */ +/* DesignId : ETH_DesignId_007*/ +/* Requirements : HL_ETH_SR18 */ +void EMACMIIDisable(uint32 emacBase) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN); +} + +/** + * \brief This API sets the duplex mode of operation(full/half) for MAC. + * + * \param emacBase Base address of the EMAC Module registers. + * \param duplexMode duplex mode of operation. + * duplexMode can take the following values. \n + * EMAC_DUPLEX_FULL - Full Duplex \n + * EMAC_DUPLEX_HALF - Half Duplex. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_008 */ +/* DesignId : ETH_DesignId_008*/ +/* Requirements : HL_ETH_SR21 */ +void EMACDuplexSet(uint32 emacBase, uint32 duplexMode) +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_FULLDUPLEX); + + HWREG(emacBase + EMAC_MACCONTROL) |= duplexMode; +} + +/** + * \brief API to enable the transmit in the TX Control Register + * After the transmit is enabled, any write to TXHDP of + * a channel will start transmission + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_009 */ +/* DesignId : ETH_DesignId_009*/ +/* Requirements : HL_ETH_SR21 */ +void EMACTxEnable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXEN; +} + +/** + * \brief API to disable the transmit in the TX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_010 */ +/* DesignId : ETH_DesignId_010*/ +/* Requirements : HL_ETH_SR21 */ +void EMACTxDisable(uint32 emacBase) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_TXCONTROL) = EMAC_TXCONTROL_TXDIS; +} + +/** + * \brief API to enable the receive in the RX Control Register + * After the receive is enabled, and write to RXHDP of + * a channel, the data can be received in the destination + * specified by the corresponding RX buffer descriptor. + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_011*/ +/* DesignId : ETH_DesignId_011*/ +/* Requirements : HL_ETH_SR21 */ +void EMACRxEnable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXEN; +} + +/** + * \brief API to disable the receive in the RX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_012*/ +/* DesignId : ETH_DesignId_012*/ +/* Requirements : HL_ETH_SR21 */ +void EMACRxDisable(uint32 emacBase) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_RXCONTROL) = EMAC_RXCONTROL_RXDIS; +} + +/** + * \brief API to write the TX HDP register. If transmit is enabled, + * write to the TX HDP will immediately start transmission. + * The data will be taken from the buffer pointer of the TX buffer + * descriptor written to the TX HDP + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the TX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_013*/ +/* DesignId : ETH_DesignId_013*/ +/* Requirements : HL_ETH_SR16 */ +void EMACTxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr, + uint32 channel) +{ + HWREG(emacBase + EMAC_TXHDP(channel)) = descHdr; +} + +/** + * \brief API to write the RX HDP register. If receive is enabled, + * write to the RX HDP will enable data reception to point to + * the corresponding RX buffer descriptor's buffer pointer. + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the RX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_014 */ +/* DesignId : ETH_DesignId_014*/ +/* Requirements : HL_ETH_SR16 */ +void EMACRxHdrDescPtrWrite(uint32 emacBase, uint32 descHdr, uint32 channel) +{ + HWREG(emacBase + EMAC_RXHDP(channel)) = descHdr; +} + +/** + * \brief This API Initializes the EMAC and EMAC Control modules. The + * EMAC Control module is reset, the CPPI RAM is cleared. also, + * all the interrupts are disabled. This API does not enable any + * interrupt or operation of the EMAC. + * + * \param emacCtrlBase Base Address of the EMAC Control module + * registers.\n + * \param emacBase Base address of the EMAC module registers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_015 */ +/* DesignId : ETH_DesignId_015*/ +/* Requirements : HL_ETH_SR6 */ +void EMACInit(uint32 emacCtrlBase, uint32 emacBase) +{ + uint32 cnt; + + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET) == EMAC_CONTROL_RESET) + { + } /* Wait */ + + /* Reset the EMAC Module. This clears the CPPI RAM also */ + HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET) == EMAC_SOFT_RESET ) + { + } /* Wait */ + + HWREG(emacBase + EMAC_MACCONTROL)= 0U; + HWREG(emacBase + EMAC_RXCONTROL)= 0U; + HWREG(emacBase + EMAC_TXCONTROL)= 0U; + + /* Initialize all the header descriptor pointer registers */ + for(cnt = 0U; cnt< EMAC_MAX_HEADER_DESC; cnt++) + { + HWREG(emacBase + EMAC_RXHDP(cnt)) = 0U; + HWREG(emacBase + EMAC_TXHDP(cnt)) = 0U; + HWREG(emacBase + EMAC_RXCP(cnt)) = 0U; + HWREG(emacBase + EMAC_TXCP(cnt)) = 0U; + HWREG(emacBase + EMAC_RXFREEBUFFER(cnt)) = 0xFFU; + } + /* Clear the interrupt enable for all the channels */ + HWREG(emacBase + EMAC_TXINTMASKCLEAR) = 0xFFU; + HWREG(emacBase + EMAC_RXINTMASKCLEAR) = 0xFFU; + + HWREG(emacBase + EMAC_MACHASH1) = 0U; + HWREG(emacBase + EMAC_MACHASH2) = 0U; + + HWREG(emacBase + EMAC_RXBUFFEROFFSET) = 0U; +} + +/** + * \brief Sets the MAC Address in MACSRCADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_016 */ +/* DesignId : ETH_DesignId_016*/ +/* Requirements : HL_ETH_SR7 */ +void EMACMACSrcAddrSet(uint32 emacBase, uint8 macAddr[6]) +{ + HWREG(emacBase + EMAC_MACSRCADDRHI) = ((uint32)macAddr[5U] |((uint32)macAddr[4U] << 8U) + |((uint32)macAddr[3U] << 16U) |((uint32)macAddr[2U] << 24U)); + HWREG(emacBase + EMAC_MACSRCADDRLO) = ((uint32)macAddr[1U] | ((uint32)macAddr[0U] << 8U)); +} + +/** + * \brief Sets the MAC Address in MACADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param matchFilt Match or Filter + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * matchFilt can take the following values \n + * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match + * or filter incoming packet. \n + * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n + * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_017 */ +/* DesignId : ETH_DesignId_017*/ +/* Requirements : HL_ETH_SR7 */ +void EMACMACAddrSet(uint32 emacBase, uint32 channel, uint8 macAddr[6], uint32 matchFilt) +{ + HWREG(emacBase + EMAC_MACINDEX) = channel; + + HWREG(emacBase + EMAC_MACADDRHI) = ((uint32)macAddr[5U] |((uint32)macAddr[4U] << 8U) + |((uint32)macAddr[3U] << 16U) |((uint32)macAddr[2U] << 24U)); + HWREG(emacBase + EMAC_MACADDRLO) = ((uint32)macAddr[1U] | ((uint32)macAddr[0U] << 8U) + | matchFilt | (channel << 16U)); +} + +/** + * \brief Acknowledges an interrupt processed to the EMAC Control Core. + * + * \param emacBase Base Address of the EMAC module registers. + * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control + * module. + * eoiFlag can take the following values \n + * EMAC_INT_CORE0_TX - Core 0 TX Interrupt + * EMAC_INT_CORE1_TX - Core 1 TX Interrupt + * EMAC_INT_CORE2_TX - Core 2 TX Interrupt + * EMAC_INT_CORE0_RX - Core 0 RX Interrupt + * EMAC_INT_CORE1_RX - Core 1 RX Interrupt + * EMAC_INT_CORE2_RX - Core 2 RX Interrupt + * \return None + * + **/ +/* SourceId : ETH_SourceId_018 */ +/* DesignId : ETH_DesignId_018*/ +/* Requirements : HL_ETH_SR15 */ +void EMACCoreIntAck(uint32 emacBase, uint32 eoiFlag) +{ + /* Acknowledge the EMAC Control Core */ + HWREG(emacBase + EMAC_MACEOIVECTOR) = eoiFlag; +} + +/** + * \brief Writes the the TX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_019 */ +/* DesignId : ETH_DesignId_019*/ +/* Requirements : HL_ETH_SR27 */ +void EMACTxCPWrite(uint32 emacBase, uint32 channel, uint32 comPtr) +{ + HWREG(emacBase + EMAC_TXCP(channel)) = comPtr; +} + +/** + * \brief Writes the the RX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_020 */ +/* DesignId : ETH_DesignId_020*/ +/* Requirements : HL_ETH_SR27 */ +void EMACRxCPWrite(uint32 emacBase, uint32 channel, uint32 comPtr) +{ + HWREG(emacBase + EMAC_RXCP(channel)) = comPtr; +} + +/** + * \brief Enables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_021 */ +/* DesignId : ETH_DesignId_021*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxBroadCastEnable(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADCH); + + HWREG(emacBase + EMAC_RXMBPENABLE) |= ((uint32)EMAC_RXMBPENABLE_RXBROADEN | ((uint32)channel << (uint32)EMAC_RXMBPENABLE_RXBROADCH_SHIFT)); +} + +/** + * \brief Disables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_022 */ +/* DesignId : ETH_DesignId_022*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxBroadCastDisable(uint32 emacBase, uint32 channel) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADCH); + /* Broadcast Frames are filtered. */ + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXBROADEN); +} + +/** + * \brief Enables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_023 */ +/* DesignId : ETH_DesignId_023*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxMultiCastEnable(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTCH); + + HWREG(emacBase + EMAC_RXMBPENABLE) |= ((uint32)EMAC_RXMBPENABLE_RXMULTEN |(channel)); +} + +/** + * \brief Disables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_024 */ +/* DesignId : ETH_DesignId_024*/ +/* Requirements : HL_ETH_SR28 */ +void EMACRxMultiCastDisable(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTCH); + + HWREG(emacBase + EMAC_RXMBPENABLE) &= (~(uint32)EMAC_RXMBPENABLE_RXMULTEN); +} + +/** + * \brief Enables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_025 */ +/* DesignId : ETH_DesignId_025*/ +/* Requirements : HL_ETH_SR14 */ +void EMACRxUnicastSet(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_RXUNICASTSET) |= ((uint32)1U << channel); +} + +/** + * \brief Disables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_026 */ +/* DesignId : ETH_DesignId_026*/ +/* Requirements : HL_ETH_SR14 */ +void EMACRxUnicastClear(uint32 emacBase, uint32 channel) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG(emacBase + EMAC_RXUNICASTCLEAR) |= ((uint32)1U << channel); +} + + +/** + * \brief Set the free buffers for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param nBuf Number of free buffers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_027 */ +/* DesignId : ETH_DesignId_027*/ +/* Requirements : HL_ETH_SR20 */ +void EMACNumFreeBufSet(uint32 emacBase, uint32 channel, + uint32 nBuf) +{ + HWREG(emacBase + EMAC_RXFREEBUFFER(channel)) = nBuf; +} + +/** + * \brief Gets the interrupt vectors of EMAC, which are pending + * + * \param emacBase Base Address of the EMAC module registers. + * + * \return Vectors + * + **/ +/* SourceId : ETH_SourceId_028 */ +/* DesignId : ETH_DesignId_028*/ +/* Requirements : HL_ETH_SR15 */ +uint32 EMACIntVectorGet(uint32 emacBase) +{ + return (HWREG(emacBase + EMAC_MACINVECTOR)); +} + + + +/** +* Function to setup the instance parameters inside the interface +* @param hdkif Network interface structure +* @return none. +*/ +/* SourceId : ETH_SourceId_029 */ +/* DesignId : ETH_DesignId_029*/ +/* Requirements : HL_ETH_SR6 */ +void EMACInstConfig(hdkif_t *hdkif) +{ + hdkif->emac_base = EMAC_0_BASE; + hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE; + hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE; + hdkif->mdio_base = MDIO_BASE; + hdkif->phy_addr = 1U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. */ + hdkif->phy_autoneg = &Dp83640AutoNegotiate; + hdkif->phy_partnerability = &Dp83640PartnerAbilityGet; +} + +/** +* Function to setup the link. AutoNegotiates with the phy for link +* setup and set the EMAC with the result of autonegotiation. +* @param hdkif Network interface structure. +* @return ERR_OK if everything passed +* others if not passed +*/ +/* SourceId : ETH_SourceId_030 */ +/* DesignId : ETH_DesignId_030*/ +/* Requirements : HL_ETH_SR6 */ +uint32 EMACLinkSetup(hdkif_t *hdkif) { + uint32 linkstat = EMAC_ERR_CONNECT; + uint16 partnr_ablty = 0U; + uint32 phyduplex = EMAC_DUPLEX_HALF; + volatile uint32 delay = 0xFFFFFU; + + if(Dp83640AutoNegotiate((uint32)hdkif->mdio_base, (uint32)hdkif->phy_addr, + (uint16)((uint16)DP83640_100BTX | (uint16)DP83640_100BTX_FD + | (uint16)DP83640_10BT | (uint16)DP83640_10BT_FD)) == TRUE) { + linkstat = EMAC_ERR_OK; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker (due to use of & ?) */ + (void)Dp83640PartnerAbilityGet(hdkif->mdio_base, hdkif->phy_addr, + &partnr_ablty); + + /* Check for 100 Mbps and duplex capability */ + if((partnr_ablty & DP83640_100BTX_FD) != 0U) { + phyduplex = EMAC_DUPLEX_FULL; + } + } + + + else { + linkstat = EMAC_ERR_CONNECT; + } + + /* Set the EMAC with the negotiation results if it is successful */ + if(linkstat == EMAC_ERR_OK) { + EMACDuplexSet(hdkif->emac_base, phyduplex); + } + + /* Wait for the MII to settle down */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while(delay != 0U) + { + delay--; + } + + return linkstat; +} + +/** + * \brief Perform a transmit queue teardown, that is, transmission is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_031 */ +/* DesignId : ETH_DesignId_031*/ +/* Requirements : HL_ETH_SR22 */ +void EMACTxTeardown(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_TXTEARDOWN) &= (channel); +} + +/** + * \brief Perform a receive queue teardown, that is, reception is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_032 */ +/* DesignId : ETH_DesignId_032*/ +/* Requirements : HL_ETH_SR22 */ +void EMACRxTeardown(uint32 emacBase, uint32 channel) +{ + HWREG(emacBase + EMAC_RXTEARDOWN) &= (channel); +} + + +/** + * \brief Perform multicast frame filtering using the MAC Hash Registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param hashTable The hash table which specifies which bits are to be accepted. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_033 */ +/* DesignId : ETH_DesignId_033*/ +/* Requirements : HL_ETH_SR24 */ +void EMACFrameSelect(uint32 emacBase, uint64 hashTable) +{ + HWREG(emacBase + EMAC_MACHASH1) = (uint32)(hashTable & 0xFFFFFFFFU); + HWREG(emacBase + EMAC_MACHASH2) = (uint32)(hashTable >> 32U); +} + + +/** + * \brief Sets the Transmit Queue Priority type in the MACCONTROL Register + * + * \param emacBase Base Address of the EMAC module registers. + * \param txPType The Transmit Queue Priority Type. + * 0 results in a round-robin scheme being used to select the next channel, while 1 results + * in a fixed-priority scheme( channel 7 highest priority). + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_034 */ +/* DesignId : ETH_DesignId_034*/ +/* Requirements : HL_ETH_SR25 */ +void EMACTxPrioritySelect(uint32 emacBase, uint32 txPType) +{ + + /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */ + if(txPType == 1U) + { + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_TXPTYPE)); + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_TXPTYPE; + } + else + { + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_TXPTYPE)); + } +} + + +/** + * \brief Performs a soft reset of the EMAC and EMAC Control Modules. + * + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_035 */ +/* DesignId : ETH_DesignId_035*/ +/* Requirements : HL_ETH_SR26 */ +void EMACSoftReset(uint32 emacCtrlBase, uint32 emacBase) +{ + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(emacCtrlBase + EMAC_CTRL_SOFTRESET) & EMAC_CONTROL_RESET) == EMAC_CONTROL_RESET) + { + /* Wait for the reset to complete */ + } + + /* Reset the EMAC Module. */ + HWREG(emacBase + EMAC_SOFTRESET) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(emacBase + EMAC_SOFTRESET) & EMAC_SOFT_RESET) == EMAC_SOFT_RESET ) + { + /* Wait for the Reset to complete */ + } + +} + +/** + * \brief Enable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_036 */ +/* DesignId : ETH_DesignId_036*/ +/* Requirements : HL_ETH_SR32 */ +void EMACEnableIdleState(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_CMDIDLE; +} + +/** + * \brief Disable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_037 */ +/* DesignId : ETH_DesignId_037*/ +/* Requirements : HL_ETH_SR32 */ +void EMACDisableIdleState(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)(EMAC_MACCONTROL_CMDIDLE)); +} + +/** + * \brief Enables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_038 */ +/* DesignId : ETH_DesignId_038*/ +/* Requirements : HL_ETH_SR50 */ +void EMACEnableLoopback(uint32 emacBase) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + uint32 GMIIENval=0U; + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG(emacBase + EMAC_MACCONTROL) & EMAC_MACCONTROL_GMIIEN; + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN); + + /*Enable Loopback */ + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_LOOPBACK; + + /*Restore the value of GMIIEN bit */ + HWREG(emacBase + EMAC_MACCONTROL) |= GMIIENval; +} + +/** + * \brief Disables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_039 */ +/* DesignId : ETH_DesignId_039*/ +/* Requirements : HL_ETH_SR50 */ +void EMACDisableLoopback(uint32 emacBase) +{ + uint32 GMIIENval=0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG(emacBase + EMAC_MACCONTROL) & EMAC_MACCONTROL_GMIIEN; + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_GMIIEN); + + /*Disable Loopback */ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_LOOPBACK); + + /*Restore the value of GMIIEN bit */ + HWREG(emacBase + EMAC_MACCONTROL) |= GMIIENval; +} + +/** + * \brief Enable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_040 */ +/* DesignId : ETH_DesignId_040*/ +/* Requirements : HL_ETH_SR20 */ +void EMACTxFlowControlEnable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_TXFLOWEN; +} + +/** + * \brief Disable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_041 */ +/* DesignId : ETH_DesignId_041*/ +/* Requirements : HL_ETH_SR20 */ +void EMACTxFlowControlDisable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_TXFLOWEN); +} + +/** + * \brief Enable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_042 */ +/* DesignId : ETH_DesignId_042*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxFlowControlEnable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) |= EMAC_MACCONTROL_RXBUFFERFLOWEN; +} + +/** + * \brief Disable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_043 */ +/* DesignId : ETH_DesignId_043*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxFlowControlDisable(uint32 emacBase) +{ + HWREG(emacBase + EMAC_MACCONTROL) &= (~(uint32)EMAC_MACCONTROL_RXBUFFERFLOWEN); +} + +/** + * \brief Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param threshold threshold value for issuing flow control on incoming frames for the given channel + * \return None + * + **/ +/* SourceId : ETH_SourceId_044 */ +/* DesignId : ETH_DesignId_044*/ +/* Requirements : HL_ETH_SR20 */ +void EMACRxSetFlowThreshold(uint32 emacBase, uint32 channel, uint32 threshold) +{ + HWREG(emacBase + EMAC_RXFLOWTHRESH(channel)) &= (0x0U); + HWREG(emacBase + EMAC_RXFLOWTHRESH(channel)) |= threshold; +} + +/** + * \brief This function reads the contents of the 36 network statistics registers that are present in the module. + * \param emacBase Base Address of the EMAC module registers. + * \param statRegNo The number of the register with RXGOODFRAMES (Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers and their contents. + * \return uint32 + **/ +/* SourceId : ETH_SourceId_045 */ +/* DesignId : ETH_DesignId_045*/ +/* Requirements : HL_ETH_SR29 */ +uint32 EMACReadNetStatRegisters(uint32 emacBase, uint32 statRegNo) +{ + return HWREG(emacBase + EMAC_NETSTATREGS(statRegNo)); +} + + +/** + * \brief Function to read values of Transmit Interrupt Status registers (TXINTSTATMASKED and TXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param txintstat pointer to the emac_tx_int_status Structure that will store the register values that have been read + * \return None + * + **/ +/* SourceId : ETH_SourceId_046 */ +/* DesignId : ETH_DesignId_046*/ +/* Requirements : HL_ETH_SR23 */ +void EMACTxIntStat(uint32 emacBase, uint32 channel, emac_tx_int_status_t *txintstat) +{ + txintstat->intstatmasked = (HWREG(emacBase + EMAC_TXINTSTATMASKED) & ((uint32)1U << channel)); + txintstat->intstatraw = (HWREG(emacBase + EMAC_TXINTSTATRAW) & ((uint32)1U << channel)); +} + + +/** + * \brief Function to read values of Receive Interrupt Status registers (RXINTSTATMASKED, RXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param rxintstat pointer to the emac_rx_int_status Structure that will store the register values that have been read. + * \return None + **/ +/* SourceId : ETH_SourceId_047 */ +/* DesignId : ETH_DesignId_047*/ +/* Requirements : HL_ETH_SR23 */ +void EMACRxIntStat(uint32 emacBase, uint32 channel, emac_rx_int_status_t *rxintstat) +{ + rxintstat->intstatmasked_pend = (HWREG(emacBase + EMAC_RXINTSTATMASKED) & ((uint32)0x1U << (uint32)(channel))); + rxintstat->intstatmasked_threshpend = (HWREG(emacBase + EMAC_RXINTSTATMASKED) & ((uint32)0x1U << ((uint32)0x8U + (uint32)(channel)))); + + rxintstat->intstatraw_pend = (HWREG(emacBase + EMAC_RXINTSTATRAW) & ((uint32)0x1U << (uint32)(channel))); + rxintstat->intstatraw_threshpend = (HWREG(emacBase + EMAC_RXINTSTATRAW) & ((uint32)0x1U << ((uint32)0x8U + (uint32)(channel)))); +} + + +/** + * \brief Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to the Rx Descriptors. + * + * \param hdkif network interface structure + * \return None + * + **/ +/* SourceId : ETH_SourceId_048 */ +/* DesignId : ETH_DesignId_048*/ +/* Requirements : HL_ETH_SR17,HL_ETH_SR30 */ +void EMACDMAInit(hdkif_t *hdkif) +{ + + uint32 num_bd, pbuf_cnt = 0U; + volatile emac_tx_bd_t *curr_txbd, *last_txbd; + volatile emac_rx_bd_t *curr_bd, *last_bd; + txch_t *txch_dma; + rxch_t *rxch_dma; + uint8_t *p; + + txch_dma = &(hdkif->txchptr); + + /** + * Initialize the Descriptor Memory For TX and RX + * Only single channel is supported for both TX and RX + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + txch_dma->free_head = (volatile emac_tx_bd_t*)(hdkif->emac_ctrl_ram); + txch_dma->next_bd_to_process = txch_dma->free_head; + txch_dma->active_tail = NULL; + + /* Set the number of descriptors for the channel */ + num_bd = (SIZE_EMAC_CTRL_RAM >> 1U) / sizeof(emac_tx_bd_t); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_txbd = txch_dma->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_txbd = curr_txbd; + + /* Initialize all the TX buffer Descriptors */ + while(num_bd != 0U) { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is incremented." */ + curr_txbd->next = curr_txbd + 1U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_txbd->flags_pktlen = 0U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_txbd = curr_txbd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_txbd = curr_txbd->next; + num_bd--; + } + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_txbd->next = txch_dma->free_head; + + /* Initialize the descriptors for the RX channel */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_dma = &(hdkif->rxchptr); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is incremented." */ + curr_txbd++; + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "Linked List pointer needs to be assigned." */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "Linked List pointer needs to be assigned." */ + /*SAFETYMCUSW 344 S MR:11.5 "Linked List pointer needs to be assigned to a different structure." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_dma->active_head = (volatile emac_rx_bd_t *)curr_txbd; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_dma->free_head = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = rxch_dma->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = curr_bd; + + + /* + ** Static allocation of a specific number of packet buffers as specified by MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI. + */ + + /*Commented part of allocation of pbufs need to check whether its true*/ + + for(pbuf_cnt = 0U;pbuf_cnt < MAX_RX_PBUF_ALLOC;pbuf_cnt++) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + p = pbuf_array[pbuf_cnt]; + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->bufptr = (uint32)p; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->bufoff_len = MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen = EMAC_BUF_DESC_OWNER; + if (pbuf_cnt == (MAX_RX_PBUF_ALLOC - 1U)) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = curr_bd; + + } + else + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is incremented." */ + curr_bd->next = (curr_bd + 1U); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is incremented." */ + curr_bd++; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = curr_bd; + } + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_dma->active_tail = last_bd; +} + + +/** + * \brief Initializes the EMAC module for transmission and reception. + * + * \param macaddr MAC Address of the Module. + * \param channel Channel Number. + * + * \return EMAC_ERR_OK if everything gets initialized + * EMAC_ERR_CONN in case of an error in connecting. + * + **/ +/* SourceId : ETH_SourceId_049 */ +/* DesignId : ETH_DesignId_049*/ +/* Requirements : HL_ETH_SR6 */ +uint32 EMACHWInit(uint8_t macaddr[6U]) +{ + uint32 temp, channel; + volatile uint32 phyID=0U; + volatile uint32 delay = 0xFFFU; + uint32 phyIdReadCount = 0xFFFFU; + volatile uint32 phyLinkRetries = 0xFFFFU; + hdkif_t *hdkif; + rxch_t *rxch; + uint32 retVal = EMAC_ERR_OK; + uint32 emacBase = 0U; +#if(EMAC_MII_ENABLE == 0U) + uint16 partnr_spd; +#endif + + hdkif = &hdkif_data[0U]; + EMACInstConfig(hdkif); + /* set MAC hardware address */ + for(temp = 0U; temp < EMAC_HWADDR_LEN; temp++) { + hdkif->mac_addr[temp] = macaddr[(EMAC_HWADDR_LEN - 1U) - temp]; + } + /*Initialize the EMAC, EMAC Control and MDIO modules. */ + EMACInit(hdkif->emac_ctrl_base, hdkif->emac_base); + MDIOInit(hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while(delay != 0U) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + delay--; + } + + /* Set the MAC Addresses in EMAC hardware */ + emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */ + EMACMACSrcAddrSet(emacBase, hdkif->mac_addr); + for(channel = 0U; channel < 8U; channel++) { + emacBase = hdkif->emac_base; + EMACMACAddrSet(emacBase, channel, hdkif->mac_addr, EMAC_MACADDR_MATCH); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while ((phyID == 0U) && (phyIdReadCount > 0U)) { + phyID = Dp83640IDGet(hdkif->mdio_base,hdkif->phy_addr); + phyIdReadCount--; + } + + if (0U == phyID) { + retVal = EMAC_ERR_CONNECT; + } else { + + } + + if((uint32)0U == ((MDIOPhyAliveStatusGet(hdkif->mdio_base) + >> hdkif->phy_addr) & (uint32)0x01U )) { + retVal = EMAC_ERR_CONNECT; + } else { + + } + +#if(EMAC_MII_ENABLE == 0U) + + Dp83640PartnerSpdGet(hdkif->mdio_base, hdkif->phy_addr, &partnr_spd); + if((partnr_spd & 2U)==0U) + { + EMACRMIISpeedSet(hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED); + } +#endif + + if(!Dp83640LinkStatusGet(hdkif->mdio_base, (uint32)EMAC_PHYADDRESS, (uint32)phyLinkRetries)) { + retVal = EMAC_ERR_CONNECT; + } else { + + } + + if(EMACLinkSetup(hdkif) != EMAC_ERR_OK) { + retVal = EMAC_ERR_CONNECT; + } else { + + } + + /* The transmit and receive buffer descriptors are initialized here. + * Also, packet buffers are allocated to the receive buffer descriptors. + */ + + EMACDMAInit(hdkif); + + /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/ + EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_RX); + EMACCoreIntAck(hdkif->emac_base, (uint32)EMAC_INT_CORE0_TX); + + /* Enable GMII bit in the MACCONTROL Rgister*/ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ + EMACMIIEnable(hdkif->emac_base); + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if(EMAC_BROADCAST_ENABLE) + EMACRxBroadCastEnable(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + EMACRxBroadCastDisable(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER); +#endif + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if(EMAC_UNICAST_ENABLE) + EMACRxUnicastSet(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + EMACRxUnicastClear(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER); +#endif + + /*Enable Full Duplex or Half-Duplex mode based on GUI Input. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if (EMAC_FULL_DUPLEX_ENABLE) + EMACDuplexSet(EMAC_0_BASE, (uint32)EMAC_DUPLEX_FULL); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition arameter is taken as input from GUI." */ + EMACDuplexSet(EMAC_0_BASE, (uint32)EMAC_DUPLEX_HALF); +#endif + + /* Enable Loopback based on GUI Input */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if(EMAC_LOOPBACK_ENABLE) + EMACEnableLoopback(hdkif->emac_base); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + EMACDisableLoopback(hdkif->emac_base); +#endif + + /* Enable Transmit and Transmit Interrupt */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if(EMAC_TX_ENABLE) + EMACTxEnable(hdkif->emac_base); + EMACTxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, (uint32)EMAC_CHANNELNUMBER, (uint32)EMAC_CHANNELNUMBER); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + EMACTxDisable(hdkif->emac_base); + EMACTxIntPulseDisable(hdkif->emac_base, hdkif->emac_ctrl_base, (uint32)EMAC_CHANNELNUMBER, (uint32)EMAC_CHANNELNUMBER); +#endif + + /* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP register. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if(EMAC_RX_ENABLE) + EMACNumFreeBufSet(hdkif->emac_base,(uint32)EMAC_CHANNELNUMBER , (uint32)MAX_RX_PBUF_ALLOC); + EMACRxEnable(hdkif->emac_base); + EMACRxIntPulseEnable(hdkif->emac_base, hdkif->emac_ctrl_base, (uint32)EMAC_CHANNELNUMBER, (uint32)EMAC_CHANNELNUMBER); + rxch = &(hdkif->rxchptr); + /* Write to the RX HDP for channel 0 */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32)rxch->active_head, (uint32)EMAC_CHANNELNUMBER); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from GUI." */ + EMACRxDisable(hdkif->emac_base); + EMACRxIntPulseDisable(hdkif->emac_base, hdkif->emac_ctrl_base, (uint32)EMAC_CHANNELNUMBER, (uint32)EMAC_CHANNELNUMBER); +#endif + + return retVal; +} + + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf might be + * chained. That is, one pbuf can span more than one tx buffer descriptors + * + * @param hdkif network interface structure + * @param pbuf the pbuf structure which contains the data to be sent using EMAC + * @return boolean. + * -Returns FALSE if a Null pointer was passed for transmission + * -Returns TRUE if valid data is sent and is transmitted. + */ +/* SourceId : ETH_SourceId_050 */ +/* DesignId : ETH_DesignId_050*/ +/* Requirements : HL_ETH_SR31 */ +boolean EMACTransmit(hdkif_t *hdkif, pbuf_t *pbuf) +{ + + txch_t *txch; + pbuf_t *q; + uint16 totLen; + uint16 qLen; + volatile emac_tx_bd_t *curr_bd,*active_head, *bd_end; + boolean retValue = FALSE; + if((pbuf != NULL) && (hdkif != NULL)) + { + txch = &(hdkif->txchptr); + + /* Get the buffer descriptor which is free to transmit */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = txch->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + active_head = curr_bd; + + /* Update the total packet length */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen &= (~((uint32)0xFFFFU)); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + totLen = pbuf->tot_len; + curr_bd->flags_pktlen |= (uint32)(totLen); + + /* Indicate the start of the packet */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen |= (EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER); + + + /* Copy pbuf information into TX buffer descriptors */ + q = pbuf; + while(q != NULL) + { + /* Initialize the buffer pointer and length */ + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->bufptr = (uint32)(q->payload); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + qLen = q->len; + curr_bd->bufoff_len = ((uint32)(qLen) & 0xFFFFU); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = curr_bd->next; + q = q->next; + } + + + /* Indicate the start and end of the packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + bd_end->next = NULL; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + bd_end->flags_pktlen |= EMAC_BUF_DESC_EOP; + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." */ + txch->free_head = curr_bd; + + /* For the first time, write the HDP with the filled bd */ + if(txch->active_tail == NULL) { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + EMACTxHdrDescPtrWrite(hdkif->emac_base, (uint32)(active_head), (uint32)EMAC_CHANNELNUMBER); + } + + /* + * Chain the bd's. If the DMA engine, already reached the end of the chain, + * the EOQ will be set. In that case, the HDP shall be written again. + */ + else { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = txch->active_tail; + /* Wait for the EOQ bit is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while (EMAC_BUF_DESC_EOQ != (curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)) + { + } + /* Don't write to TXHDP0 until it turns to zero */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while (((uint32)0U != *((uint32 *)0xFCF78600U))) + { + } + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->next = active_head; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + if (EMAC_BUF_DESC_EOQ == (curr_bd->flags_pktlen & EMAC_BUF_DESC_EOQ)) { + /* Write the Header Descriptor Pointer and start DMA */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + EMACTxHdrDescPtrWrite(hdkif->emac_base, (uint32)(active_head), (uint32)EMAC_CHANNELNUMBER); + } + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + txch->active_tail = bd_end; + retValue = TRUE; + } + else + { + retValue = FALSE; + } + return retValue; +} + + +/** + * Function for processing Tx buffer descriptors. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_051 */ +/* DesignId : ETH_DesignId_051*/ +/* Requirements : HL_ETH_SR15 */ +void EMACTxIntHandler(hdkif_t *hdkif) +{ + txch_t *txch_int; + volatile emac_tx_bd_t *curr_bd, *next_bd_to_process; + + txch_int = &(hdkif->txchptr); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = next_bd_to_process; + + /* Check for correct start of packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_SOP) == EMAC_BUF_DESC_SOP) { + + /* Make sure that the transmission is over */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_OWNER) == EMAC_BUF_DESC_OWNER) + { + } + + /* Traverse till the end of packet is reached */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while(((curr_bd->flags_pktlen) & EMAC_BUF_DESC_EOP) != EMAC_BUF_DESC_EOP) { + curr_bd = curr_bd->next; + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + next_bd_to_process->flags_pktlen &= ~(EMAC_BUF_DESC_SOP); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen &= ~(EMAC_BUF_DESC_EOP); + + /** + * If there are no more data transmitted, the next interrupt + * shall happen with the pbuf associated with the free_head + */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + if(curr_bd->next == NULL) { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + txch_int->next_bd_to_process = txch_int->free_head; + } + + else { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + txch_int->next_bd_to_process = curr_bd->next; + } + + /* Acknowledge the EMAC and free the corresponding pbuf */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + /*SAFETYMCUSW 344 S MR:11.5 "Address stored in pointer is passed as as an int parameter." */ + EMACTxCPWrite(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER, (uint32)curr_bd); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = next_bd_to_process; + + } + +} + + +/** + * Function for processing received packets. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_052 */ +/* DesignId : ETH_DesignId_052*/ +/* Requirements : HL_ETH_SR31 */ +void EMACReceive(hdkif_t *hdkif) +{ + rxch_t *rxch_int; + volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd; + + /* The receive structure that holds data about a particular receive channel */ + rxch_int = &(hdkif->rxchptr); + + /* Get the buffer descriptors which contain the earliest filled data */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = rxch_int->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = rxch_int->active_tail; + + /** + * Process the descriptors as long as data is available + * when the DMA is receiving data, SOP flag will be set + */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while((curr_bd->flags_pktlen & EMAC_BUF_DESC_SOP) == EMAC_BUF_DESC_SOP) { + + + /* Start processing once the packet is loaded */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + if((curr_bd->flags_pktlen & EMAC_BUF_DESC_OWNER) + != EMAC_BUF_DESC_OWNER) { + + /* this bd chain will be freed after processing */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_int->free_head = curr_bd; + + /* Get the total length of the packet. curr_bd points to the start + * of the packet. + */ + + /* + * The loop runs till it reaches the end of the packet. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + while((curr_bd->flags_pktlen & EMAC_BUF_DESC_EOP)!= EMAC_BUF_DESC_EOP) + { + /*Update the flags for the descriptor again and the length of the buffer*/ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen = (uint32)EMAC_BUF_DESC_OWNER; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->bufoff_len = (uint32)MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = curr_bd->next; + } + + /* Updating the last descriptor (which contained the EOP flag) */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->flags_pktlen = (uint32)EMAC_BUF_DESC_OWNER; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd->bufoff_len = (uint32)MAX_TRANSFER_UNIT; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_bd = curr_bd->next; + + /* Acknowledge that this packet is processed */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + EMACRxCPWrite(hdkif->emac_base, (uint32)EMAC_CHANNELNUMBER, (uint32)last_bd); + + /* The next buffer descriptor is the new head of the linked list. */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_int->active_head = curr_bd; + + /* The processed descriptor is now the tail of the linked list. */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_tail = rxch_int->active_tail; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + curr_tail->next = rxch_int->free_head; + + /* The last element in the already processed Rx descriptor chain is now the end of list. */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + last_bd->next = NULL; + + + /** + * Check if the reception has ended. If the EOQ flag is set, the NULL + * Pointer is taken by the DMA engine. So we need to write the RX HDP + * with the next descriptor. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + if((curr_tail->flags_pktlen & EMAC_BUF_DESC_EOQ) == EMAC_BUF_DESC_EOQ) { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + EMACRxHdrDescPtrWrite(hdkif->emac_base, (uint32)(rxch_int->free_head), (uint32)EMAC_CHANNELNUMBER); + } + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in this driver" */ + rxch_int->free_head = curr_bd; + rxch_int->active_tail = last_bd; + } + } +} + + +/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETH_SourceId_053 */ +/* DesignId : ETH_DesignId_053*/ +/* Requirements : HL_ETH_SR52 */ +void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE; + config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE; + config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE; + config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE; + config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE; + config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE; + config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE; + config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE; + config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE; + config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE; + config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE; + } + else + { + config_reg->TXCONTROL = HWREG(EMAC_0_BASE + EMAC_TXCONTROL); + config_reg->RXCONTROL = HWREG(EMAC_0_BASE + EMAC_RXCONTROL); + config_reg->TXINTMASKSET = HWREG(EMAC_0_BASE + EMAC_TXINTMASKSET); + config_reg->TXINTMASKCLEAR = HWREG(EMAC_0_BASE + EMAC_TXINTMASKCLEAR); + config_reg->RXINTMASKSET = HWREG(EMAC_0_BASE + EMAC_RXINTMASKSET); + config_reg->RXINTMASKCLEAR = HWREG(EMAC_0_BASE + EMAC_RXINTMASKCLEAR); + config_reg->MACSRCADDRHI = HWREG(EMAC_0_BASE + EMAC_MACSRCADDRHI); + config_reg->MACSRCADDRLO = HWREG(EMAC_0_BASE + EMAC_MACSRCADDRLO); + config_reg->MDIOCONTROL = HWREG(MDIO_0_BASE + MDIO_CONTROL); + config_reg->C0RXEN = HWREG(EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN(0U)); + config_reg->C0TXEN = HWREG(EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN(0U)); + } + +} + + + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ Index: firmware/source/eqep.c =================================================================== diff -u --- firmware/source/eqep.c (revision 0) +++ firmware/source/eqep.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,1328 @@ +/** @file eqep.c +* @brief EQEP Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the EQEP driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "eqep.h" +#include "sys_vim.h" + +/*the functions +*/ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void QEPInit(void) +* @brief Initializes the eQEP Driver +* +* This function initializes the eQEP module. +*/ +/* SourceId : EQEP_SourceId_001 */ +/* DesignId : EQEP_DesignId_001 */ +/* Requirements : HL_QEP_SR1 */ +void QEPInit(void) +{ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG1->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG1->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG1->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG1->QPOSCMP = 0x00000000U; + + /** - Clear the time base */ + eqepREG1->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG1->QUPRD = (uint32) 0x00000000U; + + /** - Clear Watchdog Timer register */ + eqepREG1->QWDTMR = (uint16) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG1->QWDPRD = (uint16) 0x0000U; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG1->QDECCTL = (uint16)((uint16)((uint16)eQEP_DIRECTION_COUNT << 14U) + | (uint16)((uint16)0U << 13U) + | (uint16)((uint16)eQEP_INDEX_PIN << 12U) + | (uint16)((uint16)eQEP_RESOLUTION_1x << 11U) + | (uint16)((uint16)0U << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)0U << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)0U << 6U) + | (uint16)((uint16)0U << 5U) + | (uint16)0x0000U); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Stobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG1->QEPCTL = (uint16)((uint16)((uint16)eQEP_MAX_POSITION << 12U) + | (uint16)((uint16)0U << 11U ) + | (uint16)((uint16)eQEP_DIRECTON_DEPENDENT << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)eQEP_RISING_EDGE << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)eQEP_RISING_EDGE << 6U) + | (uint16)((uint16)eQEP_LATCH_RISING_EDGE << 4U) + | (uint16)((uint16)eQEP_ON_POSITION_COUNTER_READ << 2U) + | (uint16)0x0000U); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG1->QPOSCTL = (uint16)((uint16)((uint16)0U << 15U) + | (uint16)((uint16)eQEP_QPOSCNT_EQ_QPSCMP << 14U) + | (uint16)((uint16)eQEP_ACTIVE_HIGH << 13U) + | (uint16)((uint16)0x000U) + | (uint16)0x0000U); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG1->QCAPCTL = (uint16)((uint16)((uint16)eQEP_PS_8 << 4U) + | (uint16)((uint16)eQEP_PS_512) + | (uint16)0x0000U); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG1->QCLR = (uint16) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG1->QEINT = (uint16)((uint16)((uint16)0U << 11U) + | (uint16)((uint16)0U << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)0U << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)0U << 6U) + | (uint16)((uint16)0U << 5U) + | (uint16)((uint16)0U << 4U) + | (uint16)((uint16)0U << 3U) + | (uint16)((uint16)0U << 2U) + | (uint16)((uint16)0U << 1U)); + + /** - Clear Capture Timer register */ + eqepREG1->QCTMR = (uint16)0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG1->QCPRD = (uint16)0x0000U; + + /** - Clear Period Latch register */ + eqepREG1->QCPRDLAT = (uint16)0x0000U; + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG2->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG2->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG2->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG2->QPOSCMP = 0U; + + /** - Clear the time base */ + eqepREG2->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG2->QUPRD = (uint32) 0U; + + /** - Clear Watchdog Timer register */ + eqepREG2->QWDTMR = (uint16) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG2->QWDPRD = (uint16) 0U; + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG2->QDECCTL = (uint16)((uint16)((uint16)eQEP_DIRECTION_COUNT << 14U) + | (uint16)((uint16)0U << 13U) + | (uint16)((uint16)eQEP_INDEX_PIN << 12U) + | (uint16)((uint16)eQEP_RESOLUTION_1x << 11U) + | (uint16)((uint16)0U << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)0U << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)0U << 6U) + | (uint16)((uint16)0U << 5U) + | (uint16)0x0000U); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Strobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG2->QEPCTL = (uint16)((uint16)((uint16)eQEP_MAX_POSITION << 12U) + | (uint16)((uint16)0U << 11U) + | (uint16)((uint16)eQEP_DIRECTON_DEPENDENT << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)eQEP_RISING_EDGE << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)eQEP_RISING_EDGE << 6U) + | (uint16)((uint16)eQEP_LATCH_RISING_EDGE << 4U) + | (uint16)((uint16)eQEP_ON_POSITION_COUNTER_READ << 2U) + | (uint16)0x0000U); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG2->QPOSCTL = (uint16)((uint16)((uint16)0U << 15U) + | (uint16)((uint16)eQEP_QPOSCNT_EQ_QPSCMP << 14U) + | (uint16)((uint16)eQEP_ACTIVE_HIGH << 13U) + | (uint16)((uint16)0U) + | (uint16)0x0000U); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG2->QCAPCTL = (uint16)((uint16)((uint16)eQEP_PS_8 << 4U) + | (uint16)((uint16)eQEP_PS_512) + | (uint16)0x0000U); + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG2->QCLR = (uint16) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG2->QEINT = (uint16)((uint16)((uint16)0U << 11U) + | (uint16)((uint16)0U << 10U) + | (uint16)((uint16)0U << 9U) + | (uint16)((uint16)0U << 8U) + | (uint16)((uint16)0U << 7U) + | (uint16)((uint16)0U << 6U) + | (uint16)((uint16)0U << 5U) + | (uint16)((uint16)0U << 4U) + | (uint16)((uint16)0U << 3U) + | (uint16)((uint16)0U << 2U) + | (uint16)((uint16)0U << 1U)); + + /** - Clear Capture Timer register */ + eqepREG2->QCTMR = (uint16)0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG2->QCPRD = (uint16)0x0000U; + + /** - Clear Period Latch register */ + eqepREG2->QCPRDLAT = (uint16)0x0000U; + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +} + +/** @brief Clears all QEP interrupt flags +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_002 */ +/* DesignId : EQEP_DesignId_002 */ +/* Requirements : HL_QEP_SR2 */ +void eqepClearAllInterruptFlags (eqepBASE_t *eqep) +{ + + eqep->QCLR = 0xfffU; + + return; +} /*end of eQEP_clear_all_interrupt_flags() function */ + +/** @brief Clears a single interrupt flag +* @param[in] eqep Handle to QEP object +* @param[in] QEINT Interrupt flag +*/ +/* SourceId : EQEP_SourceId_003 */ +/* DesignId : EQEP_DesignId_003 */ +/* Requirements : HL_QEP_SR3 */ +void eqepClearInterruptFlag (eqepBASE_t *eqep, QEINT_t QEINT_type) +{ + + eqep->QCLR |= (uint16)QEINT_type; + + return; +} /*end of eQEP_clear_interrupt_flag() function */ + +/** @brief Clears the position counter +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_004 */ +/* DesignId : EQEP_DesignId_004 */ +/* Requirements : HL_QEP_SR4 */ +void eqepClearPosnCounter (eqepBASE_t *eqep) +{ + + eqep->QPOSCNT = 0U; + + return; +} /*end of eQEP_clear_posn_counter() function */ + +/** @brief Disables all interrupts +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_005 */ +/* DesignId : EQEP_DesignId_005 */ +/* Requirements : HL_QEP_SR5 */ +void eqepDisableAllInterrupts (eqepBASE_t *eqep) +{ + + eqep->QEINT = 0U; + + return; +} /*end of eQEP_disable_all_interrupts () function */ + +/** @brief Disable capture +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_006 */ +/* DesignId : EQEP_DesignId_006 */ +/* Requirements : HL_QEP_SR6 */ +void eqepDisableCapture (eqepBASE_t *eqep) +{ + + eqep->QCAPCTL &= (uint16)~eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_disable_capture () function */ + +/** @brief Disable gating of index pulse +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_007 */ +/* DesignId : EQEP_DesignId_007 */ +/* Requirements : HL_QEP_SR7 */ +void eqepDisableGateIndex (eqepBASE_t *eqep) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_IGATE; + + return; +} /*end of eQEP_disable_gate_index () function */ + +/** @brief Disable individual interrupt +* @param[in] eqep Handle to QEP object +* @param[in] QEINT Individual interrupts +*/ +/* SourceId : EQEP_SourceId_008 */ +/* DesignId : EQEP_DesignId_008 */ +/* Requirements : HL_QEP_SR8 */ +void eqepDisableInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type) +{ + + eqep->QEINT &= (uint16)~(uint16)QEINT_type; + + return; +} /*end of eQEP_disable_interrupt */ + +/** @brief Disable position compare +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_009 */ +/* DesignId : EQEP_DesignId_009 */ +/* Requirements : HL_QEP_SR9 */ +void eqepDisablePosnCompare (eqepBASE_t *eqep) +{ + + eqep->QPOSCTL &= (uint16)~eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_disable_posn_compare () function */ + +/** @brief Disable position compare shadowing +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_010 */ +/* DesignId : EQEP_DesignId_010 */ +/* Requirements : HL_QEP_SR10 */ +void eqepDisablePosnCompareShadow (eqepBASE_t *eqep) +{ + + eqep->QPOSCTL &= (uint16)~eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_disable_posn_compare_shadow () function */ + +/** @brief Disable output sync pulse +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_011 */ +/* DesignId : EQEP_DesignId_011 */ +/* Requirements : HL_QEP_SR11 */ +void eqepDisableSyncOut (eqepBASE_t *eqep) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_disable_sync_out () function */ + +/** @brief Disable unit timer +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_012 */ +/* DesignId : EQEP_DesignId_012 */ +/* Requirements : HL_QEP_SR12 */ +void eqepDisableUnitTimer (eqepBASE_t *eqep) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_disable_unit_timer () function */ + +/** @brief Disable watchdog timer +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_013 */ +/* DesignId : EQEP_DesignId_013 */ +/* Requirements : HL_QEP_SR13 */ +void eqepDisableWatchdog (eqepBASE_t *eqep) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_disable_watchdog () function */ + +/** @brief Enable capture +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_014 */ +/* DesignId : EQEP_DesignId_014 */ +/* Requirements : HL_QEP_SR14 */ +void eqepEnableCapture (eqepBASE_t *eqep) +{ + + eqep->QCAPCTL |= eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_enable_capture () function */ + +/** @brief Enable counter +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_015 */ +/* DesignId : EQEP_DesignId_015 */ +/* Requirements : HL_QEP_SR15 */ +void eqepEnableCounter (eqepBASE_t *eqep) +{ + + eqep->QEPCTL |= eQEP_QEPCTL_QPEN; + + return; +} /*end of eQEP_enable_counter () function */ + +/** @brief Enable gating of index pulse +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_016 */ +/* DesignId : EQEP_DesignId_016 */ +/* Requirements : HL_QEP_SR16 */ +void eqepEnableGateIndex (eqepBASE_t *eqep) +{ + + eqep->QDECCTL |= (uint16)eQEP_Igate_Enable; + + return; +} /*end of eQEP_enable_gate_index () function */ + +/** @brief Enable individual interrupt +* @param[in] eqep Handle to QEP object +* @param[in] QEINT_type Individual interrupts +*/ +/* SourceId : EQEP_SourceId_017 */ +/* DesignId : EQEP_DesignId_017 */ +/* Requirements : HL_QEP_SR17 */ +void eqepEnableInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type) +{ + + eqep->QEINT |= (uint16)QEINT_type; + + return; +} /*end of eQEP_enable_interrupt () function */ + +/** @brief Enable position compare +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_018 */ +/* DesignId : EQEP_DesignId_018 */ +/* Requirements : HL_QEP_SR18 */ +void eqepEnablePosnCompare (eqepBASE_t *eqep) +{ + + eqep->QPOSCTL |= eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_enable_posn_compare () function */ + +/** @brief Enable position compare shadowing +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_019 */ +/* DesignId : EQEP_DesignId_019 */ +/* Requirements : HL_QEP_SR19 */ +void eqepEnablePosnCompareShadow (eqepBASE_t *eqep) +{ + + eqep->QPOSCTL |= eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_enable_posn_compare_shadow () function */ + +/** @brief Enable output sync pulse +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_020 */ +/* DesignId : EQEP_DesignId_020 */ +/* Requirements : HL_QEP_SR46 */ +void eqepEnableSyncOut (eqepBASE_t *eqep) +{ + + eqep->QDECCTL |= eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_enable_sync_out () function */ + +/** @brief Enable unit timer +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_021 */ +/* DesignId : EQEP_DesignId_021 */ +/* Requirements : HL_QEP_SR20 */ +void eqepEnableUnitTimer (eqepBASE_t *eqep) +{ + + eqep->QEPCTL |= eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_enable_unit_timer () function */ + +/** @brief Enable watchdog timer +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_022 */ +/* DesignId : EQEP_DesignId_022 */ +/* Requirements : HL_QEP_SR21 */ +void eqepEnableWatchdog (eqepBASE_t *eqep) +{ + + eqep->QEPCTL |= eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_enable_watchdog () function */ + +/** @brief Manually force QEP interrupt +* @param[in] eqep Handle to QEP object +* @param[in] QEINT Individual interrupt +*/ +/* SourceId : EQEP_SourceId_023 */ +/* DesignId : EQEP_DesignId_023 */ +/* Requirements : HL_QEP_SR22 */ +void eqepForceInterrupt (eqepBASE_t *eqep, QEINT_t QEINT_type) +{ + + eqep->QFRC |= (uint16)QEINT_type; + + return; +} /*end of eQEP_force_interrupt () function */ + + +/** @brief Reads capture period latch +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_024 */ +/* DesignId : EQEP_DesignId_024 */ +/* Requirements : HL_QEP_SR23 */ +uint16 eqepReadCapturePeriodLatch (eqepBASE_t *eqep) +{ + return eqep->QCPRDLAT; +} /*end of eQEP_read_capture_period_latch () function */ + +/** @brief Reads timer latch +* @param[in] eqep Handle to QEP object +* @return Timer value +*/ +/* SourceId : EQEP_SourceId_025 */ +/* DesignId : EQEP_DesignId_025 */ +/* Requirements : HL_QEP_SR24 */ +uint16 eqepReadCaptureTimerLatch (eqepBASE_t *eqep) +{ + return eqep->QCTMRLAT; +} /*end of eQEP_read_capture_timer_latch () function */ + +/** @brief Reads interrupt flag value +* @param[in] eqep Handle to QEP object +* @param[in] QEINT Which interrupt to interrogate +* @return Interrupt flag value +*/ +/* SourceId : EQEP_SourceId_064 */ +/* DesignId : EQEP_DesignId_064 */ +/* Requirements : HL_QEP_SR25 */ +uint16 eqepReadInterruptFlag (eqepBASE_t *eqep, QEINT_t QEINT_type) +{ + return (uint16) (eqep->QFLG & (uint16)QEINT_type); +} /*end of eQEP_read_interrupt_flag () function */ + +/** @brief Reads position compare register +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_026 */ +/* DesignId : EQEP_DesignId_026 */ +/* Requirements : HL_QEP_SR26 */ +uint32 eqepReadPosnCompare (eqepBASE_t *eqep) +{ + + return eqep->QPOSCMP; +} /*end of eQEP_read_posn_compare () function */ + +/** @brief Reads position counter +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_027 */ +/* DesignId : EQEP_DesignId_027 */ +/* Requirements : HL_QEP_SR27 */ +uint32 eqepReadPosnCount (eqepBASE_t *eqep) +{ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + return eqep->QPOSCNT; +} /*end of eQEP_read_posn_count () function */ + +/** @brief Reads position counter value index pulse latch register +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_028 */ +/* DesignId : EQEP_DesignId_028 */ +/* Requirements : HL_QEP_SR28 */ +uint32 eqepReadPosnIndexLatch (eqepBASE_t *eqep) +{ + + return eqep->QPOSILAT; +} /*end of eQEP_read_posn_index_latch () function */ + +/** @brief Reads position counter value +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_029 */ +/* DesignId : EQEP_DesignId_029 */ +/* Requirements : HL_QEP_SR29 */ +uint32 eqepReadPosnLatch (eqepBASE_t *eqep) +{ + + return eqep->QPOSLAT; +} /*end of eQEP_read_posn_latch () function */ + +/** @brief Reads position strobe latch +* @param[in] eqep Handle to QEP object +* @return Counter value +*/ +/* SourceId : EQEP_SourceId_030 */ +/* DesignId : EQEP_DesignId_030 */ +/* Requirements : HL_QEP_SR30 */ +uint32 eqepReadPosnStrobeLatch (eqepBASE_t *eqep) +{ + + return eqep->QPOSSLAT; +} /*end of eQEP_read_posn_strobe_latch () function */ + +/** @brief Reads status register +* @param[in] eqep Handle to QEP object +* @return Status register value +*/ +/* SourceId : EQEP_SourceId_031 */ +/* DesignId : EQEP_DesignId_031 */ +/* Requirements : HL_QEP_SR31 */ +uint16 eqepReadStatus (eqepBASE_t *eqep) +{ + + return eqep->QEPSTS; +} /*end of eqepReadStatus () function */ + +/** @brief Resets counter +* @param[in] eqep Handle to QEP object +*/ +/* SourceId : EQEP_SourceId_032 */ +/* DesignId : EQEP_DesignId_032 */ +/* Requirements : HL_QEP_SR32 */ +void eqepResetCounter (eqepBASE_t *eqep) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_QPEN; + + return; +} /*end of eqepResetCounter () function */ + +/** @brief Sets capture latch mode +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Qclm capture latch mode +*/ +/* SourceId : EQEP_SourceId_033 */ +/* DesignId : EQEP_DesignId_033 */ +/* Requirements : HL_QEP_SR33 */ +void eqepSetCaptureLatchMode (eqepBASE_t *eqep, QEPCTL_Qclm_t QEPCTL_Qclm) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_QCLM; + eqep->QEPCTL |= QEPCTL_Qclm; + + return; +} /*end of eqepSetCaptureLatchMode () function */ + +/** @brief Sets capture period +* @param[in] eqep Handle to QEP object +* @param[in] period Capture period +*/ +/* SourceId : EQEP_SourceId_034 */ +/* DesignId : EQEP_DesignId_034 */ +/* Requirements : HL_QEP_SR34 */ +void eqepSetCapturePeriod (eqepBASE_t *eqep, uint16 period) +{ + + eqep->QCPRD = period; + + return; +} /*end of eqepSetCapturePeriod () function */ + +/** @brief Sets capture pre-scaler +* @param[in] eqep Handle to QEP object +* @param[in] QCAPCTL_Ccps Capture pre-scaler +*/ +/* SourceId : EQEP_SourceId_035 */ +/* DesignId : EQEP_DesignId_035 */ +/* Requirements : HL_QEP_SR35 */ +void eqepSetCapturePrescale (eqepBASE_t *eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps) +{ + + eqep->QCAPCTL &= (uint16)~eQEP_QCAPCTL_CCPS; + eqep->QCAPCTL |= QCAPCTL_Ccps; +} /*end of eqepSetCapturePrescale () function */ + +/** @brief Sets emulation control +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Freesoft Emulation control bits +*/ +/* SourceId : EQEP_SourceId_036 */ +/* DesignId : EQEP_DesignId_036 */ +/* Requirements : HL_QEP_SR36 */ +void eqepSetEmuControl (eqepBASE_t *eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_FREESOFT; + eqep->QEPCTL |= QEPCTL_Freesoft; + + return; +} /*end of eqepSetEmuControl () function */ + +/** @brief Sets external clock rate +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Xcr External clock rate +*/ +/* SourceId : EQEP_SourceId_037 */ +/* DesignId : EQEP_DesignId_037 */ +/* Requirements : HL_QEP_SR37 */ +void eqepSetExtClockRate (eqepBASE_t *eqep, eQEP_Xcr_t eQEP_Xcr) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_XCR; + eqep->QDECCTL |= (uint16)eQEP_Xcr; + + return; +} /*end of eqepSetExtClockRate () function */ + +/** @brief Sets the event which initializes the counter register +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Iei Index event +*/ +/* SourceId : EQEP_SourceId_038 */ +/* DesignId : EQEP_DesignId_038 */ +/* Requirements : HL_QEP_SR38 */ +void eqepSetIndexEventInit (eqepBASE_t *eqep, QEPCTL_Iei_t QEPCTL_Iei) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_IEI; + eqep->QEPCTL |= (uint16)QEPCTL_Iei; + + return; +} /*end of eqepSetIndexEventInit () function */ + +/** @brief Sets the index event which latches the position counter +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Iel Latch event +*/ +/* SourceId : EQEP_SourceId_039 */ +/* DesignId : EQEP_DesignId_039 */ +/* Requirements : HL_QEP_SR39 */ +void eqepSetIndexEventLatch (eqepBASE_t *eqep, QEPCTL_Iel_t QEPCTL_Iel) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_IEL; + eqep->QEPCTL |= QEPCTL_Iel; + + return; +} /*end of eqepSetIndexEventLatch */ + +/** @brief Sets index polarity +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Qip Index polarity +*/ +/* SourceId : EQEP_SourceId_040 */ +/* DesignId : EQEP_DesignId_040 */ +/* Requirements : HL_QEP_SR40 */ +void eqepSetIndexPolarity (eqepBASE_t *eqep, eQEP_Qip_t eQEP_Qip) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_QIP; + eqep->QDECCTL |= eQEP_Qip; + + return; +} /*end of eqepSetIndexPolarity () function */ + +/** @brief Sets max position count +* @param[in] eqep Handle to QEP object +* @param[in] max_count Maximum counter value +*/ +/* SourceId : EQEP_SourceId_041 */ +/* DesignId : EQEP_DesignId_041 */ +/* Requirements : HL_QEP_SR41 */ +void eqepSetMaxPosnCount (eqepBASE_t *eqep, uint32 max_count) +{ + + eqep->QPOSMAX = max_count; + + return; +} /*end of eqepSetMaxPosnCount () function */ + +/** @brief Sets output pulse width when a match occur +* @param[in] eqep Handle to QEP object +* @param[in] pulse_width Pulse width value +*/ +/* SourceId : EQEP_SourceId_042 */ +/* DesignId : EQEP_DesignId_042 */ +/* Requirements : HL_QEP_SR42 */ +void eqepSetPosnComparePulseWidth (eqepBASE_t *eqep, uint16 pulse_width) +{ + + uint16 pulse_width_masked; + + pulse_width_masked = pulse_width & 4095U; + eqep->QPOSCTL &= (uint16)~eQEP_QPOSCTL_PCSPW; + eqep->QPOSCTL |= pulse_width_masked; + + return; +} /*end of eqepSetPosnComparePulseWidth () function */ + +/** @brief Sets position compare shadow load mode +* @param[in] eqep Handle to QEP object +* @param[in] QPOSCTL_Pcload PC load event +*/ +/* SourceId : EQEP_SourceId_043 */ +/* DesignId : EQEP_DesignId_043 */ +/* Requirements : HL_QEP_SR43 */ +void eqepSetPosnCompareShadowLoad (eqepBASE_t *eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload) +{ + + eqep->QPOSCTL &= (uint16)~eQEP_QPOSCTL_PCLOAD; + eqep->QPOSCTL |= (uint16)QPOSCTL_Pcload; + + return; +} /*end of eqepSetPosnCompareShadowLoad () function */ + +/** @brief Sets position counter reset mode +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Pcrm Position counter reset mode +*/ +/* SourceId : EQEP_SourceId_044 */ +/* DesignId : EQEP_DesignId_044 */ +/* Requirements : HL_QEP_SR44 */ +void eqepSetPosnCountResetMode (eqepBASE_t *eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_PCRM; + eqep->QEPCTL |= (uint16)QEPCTL_Pcrm; + + return; +} /*end of eqepSetPosnCountResetMode () function */ + +/** @brief Sets initial position counter value +* @param[in] eqep Handle to QEP object +* @param[in] init_count initial counter value +*/ +/* SourceId : EQEP_SourceId_045 */ +/* DesignId : EQEP_DesignId_045 */ +/* Requirements : HL_QEP_SR45 */ +void eqepSetPosnInitCount (eqepBASE_t *eqep, uint32 init_count) +{ + + eqep->QPOSINIT = init_count; + + return; +} /*end of eqepSetPosnInitCount () function */ + +/** @brief Selects whether index or strobe pin is used for sync output +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_SPsel Selected pin +*/ +/* SourceId : EQEP_SourceId_046 */ +/* DesignId : EQEP_DesignId_046 */ +/* Requirements : HL_QEP_SR47 */ +void eqepSetSelectSyncPin (eqepBASE_t *eqep, eQEP_Spsel_t eQEP_SPsel) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_SPSEL; + eqep->QDECCTL |= (uint16)eQEP_SPsel; + + return; +} /*end of eQEP_set_select_sync_pin () function */ + +/** @brief Determines if software initialization of position counter enabled +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Swi Enable/disable position counter initialization +*/ +/* SourceId : EQEP_SourceId_047 */ +/* DesignId : EQEP_DesignId_047 */ +/* Requirements : HL_QEP_SR48 */ +void eqepSetSoftInit (eqepBASE_t *eqep, QEPCTL_Swi_t QEPCTL_Swi) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_SWI; + eqep->QEPCTL |= (uint16)QEPCTL_Swi; + + return; +} /*end of eQEP_set_soft_init () function */ + +/** @brief Determines strobe initialization of position counter +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Sei Strobe initialization of position counter (disabled, rising edge of QEPI) or rising/falling depending on direction +*/ +/* SourceId : EQEP_SourceId_048 */ +/* DesignId : EQEP_DesignId_048 */ +/* Requirements : HL_QEP_SR49 */ +void eqepSetStrobeEventInit (eqepBASE_t *eqep, QEPCTL_Sei_t QEPCTL_Sei) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_SEI; + eqep->QEPCTL |= (uint16)QEPCTL_Sei; + + return; +} /*end of eQEP_set_strobe_event_init () function */ + +/** @brief Sets up strobe latch of position counter +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Sel Sets strobe latch of position counter +*/ +/* SourceId : EQEP_SourceId_049 */ +/* DesignId : EQEP_DesignId_049 */ +/* Requirements : HL_QEP_SR50 */ +void eqepSetStrobeEventLatch (eqepBASE_t *eqep, QEPCTL_Sel_t QEPCTL_Sel) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= QEPCTL_Sel; + + return; +} /*end of eQEP_set_strobe_event_latch () function */ + +/** @brief Sets up strobe polarity +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Qsp Strobe polarity +*/ +/* SourceId : EQEP_SourceId_050 */ +/* DesignId : EQEP_DesignId_050 */ +/* Requirements : HL_QEP_SR51 */ +void eqepSetStrobePolarity (eqepBASE_t *eqep, eQEP_Qsp_t eQEP_Qsp) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_QSP; + eqep->QDECCTL |= eQEP_Qsp; + + return; +} /*end of eqepSetStrobePolarity () function */ + +/** @brief Sets up swapping of A/B channels +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Swap Swap/don't swap A/B channels +*/ +/* SourceId : EQEP_SourceId_051 */ +/* DesignId : EQEP_DesignId_051 */ +/* Requirements : HL_QEP_SR52 */ +void eqepSetSwapQuadInputs (eqepBASE_t *eqep, eQEP_Swap_t eQEP_Swap) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_SWAP; + eqep->QDECCTL |= (uint16)eQEP_Swap; + + return; +} /*end of eqepSetSwapQuadInputs () function */ + +/** @brief Sets sync output compare polarity +* @param[in] eqep Handle to QEP object +* @param[in] QPOSCTL_Pcpol Polarity of sync output +*/ +/* SourceId : EQEP_SourceId_052 */ +/* DesignId : EQEP_DesignId_052 */ +/* Requirements : HL_QEP_SR53 */ +void eqepSetSynchOutputComparePolarity (eqepBASE_t *eqep, QPOSCTL_Pcpol_t QPOSCTL_Pcpol) +{ + + eqep->QPOSCTL &= (uint16)~eQEP_QPOSCTL_PCPOL; + eqep->QPOSCTL |= (uint16)QPOSCTL_Pcpol; + + return; +} /*end of eqepSetSynchOutputComparePolarity () function */ + +/** @brief Sets unit timer period +* @param[in] eqep Handle to QEP object +* @param[in] unit_period Unit period +*/ +/* SourceId : EQEP_SourceId_053 */ +/* DesignId : EQEP_DesignId_053 */ +/* Requirements : HL_QEP_SR54 */ +void eqepSetUnitPeriod (eqepBASE_t *eqep, uint32 unit_period) +{ + + eqep->QUPRD = unit_period; + + return; +} /*end of eqepSetUnitPeriod () function */ + +/** @brief Sets unit timer prescaling +* @param[in] eqep Handle to QEP object +* @param[in] QCAPCTL_Upps Unit timer prescaling +*/ +/* SourceId : EQEP_SourceId_054 */ +/* DesignId : EQEP_DesignId_054 */ +/* Requirements : HL_QEP_SR55 */ +void eqepSetUnitPosnPrescale (eqepBASE_t *eqep, QCAPCTL_Upps_t QCAPCTL_Upps) +{ + + eqep->QCAPCTL &= (uint16)~eQEP_QCAPCTL_UPPS; + eqep->QCAPCTL |= (uint16)QCAPCTL_Upps; + + return; +} /*end of eqepSetUnitPosnPrescale () function */ + +/** @brief Sets watchdog period +* @param[in] eqep Handle to QEP object +* @param[in] watchdog_period Watchdog period +*/ +/* SourceId : EQEP_SourceId_055 */ +/* DesignId : EQEP_DesignId_055 */ +/* Requirements : HL_QEP_SR56 */ +void eqepSetWatchdogPeriod (eqepBASE_t *eqep, uint16 watchdog_period) +{ + + eqep->QWDPRD = watchdog_period; + + return; +} /*end of eqepSetWatchdogPeriod () function */ + +/** @brief Sets strobe event latch +* @param[in] eqep Handle to QEP object +* @param[in] QEPCTL_Sel Sets strobe latch of position counter +*/ +/* SourceId : EQEP_SourceId_056 */ +/* DesignId : EQEP_DesignId_056 */ +/* Requirements : HL_QEP_SR57 */ +void eqepSetupStrobeEventLatch (eqepBASE_t *eqep, QEPCTL_Sel_t QEPCTL_Sel) +{ + + eqep->QEPCTL &= (uint16)~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= (uint16)QEPCTL_Sel; + + return; +} /*end of eqepSetupStrobeEventLatch () function */ + +/** @brief Sets A polarity +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Qap Channel A polarity +*/ +/* SourceId : EQEP_SourceId_057 */ +/* DesignId : EQEP_DesignId_057 */ +/* Requirements : HL_QEP_SR58 */ +void eqepSetAPolarity (eqepBASE_t *eqep, eQEP_Qap_t eQEP_Qap) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_QAP; + eqep->QDECCTL |= (uint16)eQEP_Qap; + + return; +} /*end of eqepSetAPolarity () function */ + +/** @brief Sets B polarity +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Qbp Channel B polarity +*/ +/* SourceId : EQEP_SourceId_058 */ +/* DesignId : EQEP_DesignId_058 */ +/* Requirements : HL_QEP_SR59 */ +void eqepSetBPolarity (eqepBASE_t *eqep, eQEP_Qbp_t eQEP_Qbp) +{ + + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_QBP; + eqep->QDECCTL |= (uint16)eQEP_Qbp; + + return; +} /*end of eQEP_set_B_polarity () function */ + +/** @brief Set QEP counting mode +* @param[in] eqep Handle to QEP object +* @param[in] eQEP_Qsrc Sets QEP counting mode +*/ +/* SourceId : EQEP_SourceId_059 */ +/* DesignId : EQEP_DesignId_059 */ +/* Requirements : HL_QEP_SR60*/ +void eqepSetQEPSource (eqepBASE_t *eqep, eQEP_Qsrc_t eQEP_Qsrc) +{ + + /* set the value */ + eqep->QDECCTL &= (uint16)~eQEP_QDECCTL_QSRC; + eqep->QDECCTL |= (uint16)eQEP_Qsrc; + + return; +} /*end of eQEP_set_eQEP_source () function */ + +/** @brief Writes a value to the position compare register +* @param[in] eqep Handle to QEP object +* @param[in] posn Position compare register value +*/ +/* SourceId : EQEP_SourceId_060 */ +/* DesignId : EQEP_DesignId_060 */ +/* Requirements : HL_QEP_SR61 */ +void eqepWritePosnCompare (eqepBASE_t *eqep, uint32 posn) +{ + + eqep->QPOSCMP = posn; + + return; +} /*end of eQEP_write_posn_compare () function */ + +/** @fn void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : EQEP_SourceId_061 */ +/* DesignId : EQEP_DesignId_061 */ +/* Requirements : HL_QEP_SR63 */ +void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_QPOSINIT = EQEP1_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP1_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP1_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP1_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP1_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP1_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP1_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP1_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP1_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP1_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG1->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG1->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG1->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG1->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG1->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG1->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG1->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG1->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG1->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG1->QEINT; + } +} + +/** @fn void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : EQEP_SourceId_062 */ +/* DesignId : EQEP_DesignId_062 */ +/* Requirements : HL_QEP_SR63 */ +void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_QPOSINIT = EQEP2_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP2_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP2_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP2_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP2_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP2_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP2_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP2_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP2_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP2_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG2->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG2->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG2->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG2->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG2->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG2->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG2->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG2->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG2->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG2->QEINT; + } +} + + + +/*end of file*/ Index: firmware/source/etpwm.c =================================================================== diff -u --- firmware/source/etpwm.c (revision 0) +++ firmware/source/etpwm.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,2230 @@ +/** @file etpwm.c +* @brief ETPWM Driver Source File +* @date 11-Dec-2018 +* @version 04.07.01 +* +* This file contains: +* - API Functions +* - Interrupt Handlers +* . +* which are relevant for the ETPWM driver. +*/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + +#include "etpwm.h" +#include "pinmux.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + + +/** @fn void etpwmInit(void) +* @brief Initializes the eTPWM Driver +* +* This function initializes the eTPWM module. +* +* @note This function sets the time-base counters in up-count mode. +* Application can configure the module in a different mode using other functions in this driver.(Sample code provided in the examples folder) +* In that case, application need not call etpwmInit function. +* pinmuxInit needs to be called before this function. +* +*/ +/* SourceId : ETPWM_SourceId_001 */ +/* DesignId : ETPWM_DesignId_001 */ +/* Requirements : HL_EPWM_SR1 */ +void etpwmInit(void) +{ +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + + /** @b initialize @b ETPWM1 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG1->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG1->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG1->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG1->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG1->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG1->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG1->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG1->DBFED = 1U ; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG1->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG1->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG1->ETSEL & 0x0007U) != 0U) + { + etpwmREG1->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG1->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG1->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG1->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM2 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG2->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG2->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG2->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG2->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG2->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG2->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG2->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG2->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG2->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG2->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG2->ETSEL & 0x0007U) != 0U) + { + etpwmREG2->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG2->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG2->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG2->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM3 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG3->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG3->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG3->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG3->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG3->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG3->DBCTL = ((uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG3->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG3->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG3->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + + /** - Sets up the event for interrupt */ + etpwmREG3->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG3->ETSEL & 0x0007U) != 0U) + { + etpwmREG3->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG3->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG3->ETSEL |= ((uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U)); + + /** - Sets up the ADC SOC period */ + etpwmREG3->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM4 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG4->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG4->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG4->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG4->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG4->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG4->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG4->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG4->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG4->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG4->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG4->ETSEL & 0x0007U) != 0U) + { + etpwmREG4->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG4->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG4->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM5 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG5->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG5->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG5->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG5->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG5->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG5->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG5->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG5->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG5->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG5->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG5->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + + /** - Set trip source enable */ + etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG5->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG5->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG5->ETSEL & 0x0007U) != 0U) + { + etpwmREG5->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG5->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG5->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG5->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM6 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG6->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG6->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG6->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG6->CMPB = 50U; + + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG6->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG6->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG6->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG6->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG6->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + + /** - Set trip source enable */ + etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG6->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + + /** - Sets up the event for interrupt */ + etpwmREG6->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG6->ETSEL & 0x0007U) != 0U) + { + etpwmREG6->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG6->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG6->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG6->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + /** @b initialize @b ETPWM7 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG7->TBCTL = (uint16)0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG7->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG7->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG7->CMPB = 50U; + + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ + etpwmREG7->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 4U)); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ + etpwmREG7->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) + | (uint16)((uint16)ActionQual_Clear << 8U)); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG7->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ + | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ + | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ + | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG7->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG7->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ + | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ + | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ + + + /** - Set trip source enable */ + etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG7->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG7->ETSEL = (uint16)NO_EVENT; + + if ((etpwmREG7->ETSEL & 0x0007U) != 0U) + { + etpwmREG7->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG7->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG7->ETSEL |= (uint16)(0x0000U) + | (uint16)(0x0000U) + | (uint16)((uint16)DCAEVT1 << 8U) + | (uint16)((uint16)DCBEVT1 << 12U); + + /** - Sets up the ADC SOC period */ + etpwmREG7->ETPS |= ((uint16)((uint16)1U << 8U) + | (uint16)((uint16)1U << 12U)); + + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +} + +/** @fn void etpwmStartTBCLK() +* @brief Start the time-base clocks of all eTPWMx modules +* +* This function starts the time-base clocks of all eTPWMx modules. +*/ +/* SourceId : ETPWM_SourceId_002 */ +/* DesignId : ETPWM_DesignId_002 */ +/* Requirements : HL_EPWM_SR36 */ +void etpwmStartTBCLK(void) +{ + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_ON); + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmStopTBCLK() +* @brief Stop the time-base clocks of all eTPWMx modules +* +* This function stops the time-base clocks of all eTPWMx modules. +*/ +/* SourceId : ETPWM_SourceId_003 */ +/* DesignId : ETPWM_DesignId_003 */ +/* Requirements : HL_EPWM_SR36 */ +void etpwmStopTBCLK(void) +{ + /* Enable Pin Muxing */ + kickerReg->KICKER0 = 0x83E70B13U; + kickerReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMMR37 = (pinMuxReg->PINMMR37 & PINMUX_ETPWM_TBCLK_SYNC_MASK) | (PINMUX_ETPWM_TBCLK_SYNC_OFF); + + /* Disable Pin Muxing */ + kickerReg->KICKER0 = 0x00000000U; + kickerReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv) +* @brief Sets the Time-base Clock divider +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param clkdiv Time-base clock divider +* - ClkDiv_by_1 +* - ClkDiv_by_2 +* - ClkDiv_by_4 +* - ClkDiv_by_8 +* - ClkDiv_by_16 +* - ClkDiv_by_32 +* - ClkDiv_by_64 +* - ClkDiv_by_128 +* @param hspclkdiv High Speed Time-base clock divider +* - HspClkDiv_by_1 +* - HspClkDiv_by_2 +* - HspClkDiv_by_4 +* - HspClkDiv_by_6 +* - HspClkDiv_by_8 +* - HspClkDiv_by_10 +* - HspClkDiv_by_12 +* - HspClkDiv_by_14 +* +* This function sets the TimeBase Clock and the High Speed time base clock divider +* TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV) +*/ +/* SourceId : ETPWM_SourceId_004 */ +/* DesignId : ETPWM_DesignId_004 */ +/* Requirements : HL_EPWM_SR2 */ +void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t hspclkdiv) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x1F80U; + etpwm->TBCTL |= (uint16)clkdiv | (uint16)hspclkdiv; +} + +/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) +* @brief Sets period of timebase counter +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param period 16-bit Time-base period +* +* This function sets period of timebase counter +*/ +/* SourceId : ETPWM_SourceId_005 */ +/* DesignId : ETPWM_DesignId_005 */ +/* Requirements : HL_EPWM_SR3 */ +void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) +{ + etpwm->TBPRD = period; +} + +/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) +* @brief Sets timebase counter +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param count 16-bit Counter value +* +* This function sets the timebase counter +*/ +/* SourceId : ETPWM_SourceId_006 */ +/* DesignId : ETPWM_DesignId_006 */ +/* Requirements : HL_EPWM_SR4 */ +void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) +{ + etpwm->TBCTR = count; +} + +/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for time-base period register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for time-base period register +*/ +/* SourceId : ETPWM_SourceId_007 */ +/* DesignId : ETPWM_DesignId_007 */ +/* Requirements : HL_EPWM_SR5 */ +void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL |= 0x0008U; +} + +/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +* @brief Enable shadow mode for time-base period register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function enables shadow mode for time-base period register +*/ +/* SourceId : ETPWM_SourceId_008 */ +/* DesignId : ETPWM_DesignId_008 */ +/* Requirements : HL_EPWM_SR5 */ +void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0008U; +} + +/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction) +* @brief Enable counter register load from phase register when a sync event occurs +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param phase Counter value to be loaded when a sync event occurs +* @param direction Direction of the counter after the sync event (Applied only if counter is in updown-count mode, ignores otherwise) +* - COUNT_UP +* - COUNT_DOWN +* - Pass 0 if not applied +* +* This function enables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ETPWM_SourceId_009 */ +/* DesignId : ETPWM_DesignId_009 */ +/* Requirements : HL_EPWM_SR6 */ +void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 direction) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x2000U; + etpwm->TBCTL |= 0x0004U | direction; + etpwm->TBPHS = phase; +} + +/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) +* @brief Disable counter register load from phase register when a sync event occurs +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables counter register load from phase register when a sync event occurs +*/ +/* SourceId : ETPWM_SourceId_010 */ +/* DesignId : ETPWM_DesignId_010 */ +/* Requirements : HL_EPWM_SR6 */ +void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0004U; +} + +/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode) +* @brief Set the source of EPWMxSYNCO signal +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param syncOutSrc Synchronization Output Select +* - SyncOut_EPWMxSYNCI +* - SyncOut_CtrEqZero +* - SyncOut_CtrEqCmpB +* - SyncOut_Disable +* +* This function sets the source of synchronization output signal +*/ +/* SourceId : ETPWM_SourceId_011 */ +/* DesignId : ETPWM_DesignId_011 */ +/* Requirements : HL_EPWM_SR7 */ +void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncOut_t syncOutSrc) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0030U; + etpwm->TBCTL |= syncOutSrc; +} + +/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) +* @brief Set the time-base counter mode +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param countermode Counter Mode +* - CounterMode_Up +* - Countermode_Down +* - CounterMode_UpDown +* - CounterMode_Stop +* +* This function sets the time-base counter mode of operation. +*/ +/* SourceId : ETPWM_SourceId_012 */ +/* DesignId : ETPWM_DesignId_012 */ +/* Requirements : HL_EPWM_SR8 */ +void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) +{ + etpwm->TBCTL &= (uint16)~(uint16)0x0003U; + etpwm->TBCTL |= countermode; +} + +/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm) +* @brief Trigger a software synchronization pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function triggers a software synchronization pulse. SWFSYNC is valid (operates) only when EPWMxSYNCI as SyncOut +*/ +/* SourceId : ETPWM_SourceId_013 */ +/* DesignId : ETPWM_DesignId_013 */ +/* Requirements : HL_EPWM_SR9 */ +void etpwmTriggerSWSync(etpwmBASE_t *etpwm) +{ + etpwm->TBCTL |= 0x0040U; +} + +/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) +* @brief Set the pulse width modulation (ETPWM) run mode +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param runmode Run mode +* - RunMode_SoftStopAfterIncr : Stop after the next time-base counter increment +* - RunMode_SoftStopAfterDecr : Stop after the next time-base counter decrement +* - RunMode_SoftStopAfterCycle : Stop when counter completes a whole cycle +* - RunMode_FreeRun : Free-run +* +* This function select the behaviour of the ePWM time-base counter during emulation events +*/ +/* SourceId : ETPWM_SourceId_014 */ +/* DesignId : ETPWM_DesignId_014 */ +/* Requirements : HL_EPWM_SR10 */ +void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) +{ + etpwm->TBCTL &= (uint16)~(uint16)0xC000U; + etpwm->TBCTL |= runmode; +} + +/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) +* @brief Set the Compare A value +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param value 16-bit Compare A value +* +* This function sets the compare A value +*/ +/* SourceId : ETPWM_SourceId_015 */ +/* DesignId : ETPWM_DesignId_015 */ +/* Requirements : HL_EPWM_SR11 */ +void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) +{ + etpwm->CMPA = value; +} + +/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) +* @brief Set the Compare B value +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param value 16-bit Compare B value +* +* This function sets the compare B register +*/ +/* SourceId : ETPWM_SourceId_016 */ +/* DesignId : ETPWM_DesignId_016 */ +/* Requirements : HL_EPWM_SR11 */ +void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) +{ + etpwm->CMPB = value; +} + +/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +* @brief Enable shadow mode for Compare A register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode +* - LoadMode_CtrEqZero : Load on CTR = Zero +* - LoadMode_CtrEqPeriod : Load on CTR = PRD +* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD +* - LoadMode_Freeze : Freeze (no loads possible) +* +* This function enables shadow mode for Compare A register +*/ +/* SourceId : ETPWM_SourceId_017 */ +/* DesignId : ETPWM_DesignId_017 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +{ + etpwm->CMPCTL &= (uint16)~(uint16)0x0013U; + etpwm->CMPCTL |= loadmode; +} + +/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for Compare A register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for Compare A register +*/ +/* SourceId : ETPWM_SourceId_018 */ +/* DesignId : ETPWM_DesignId_018 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->CMPCTL |= 0x0010U; +} + +/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +* @brief Enable shadow mode for Compare B register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode +* - LoadMode_CtrEqZero : Load on CTR = Zero +* - LoadMode_CtrEqPeriod : Load on CTR = PRD +* - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD +* - LoadMode_Freeze : Freeze (no loads possible) +* +* This function enables shadow mode for Compare B register +*/ +/* SourceId : ETPWM_SourceId_019 */ +/* DesignId : ETPWM_DesignId_019 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) +{ + etpwm->CMPCTL &= (uint16)~(uint16)0x004CU; + etpwm->CMPCTL |= (uint16)((uint16)loadmode << 2U); +} + +/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) +* @brief Disable shadow mode for Compare B register +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables shadow mode for Compare B register +*/ +/* SourceId : ETPWM_SourceId_020 */ +/* DesignId : ETPWM_DesignId_020 */ +/* Requirements : HL_EPWM_SR12 */ +void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) +{ + etpwm->CMPCTL |= 0x0040U; +} + +/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +* @brief Configure Action Qualifier submodule to generate PWMA +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param actionqualconfig Action Qualifier configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmActionQualConfig_t configA +* configA.CtrEqZero_Action = ActionQual_Set +* configA.CtrEqPeriod_Action = ActionQual_Disabled +* configA.CtrEqCmpAUp_Action = ActionQual_Clear +* configA.CtrEqCmpADown_Action = ActionQual_Disabled +* configA.CtrEqCmpBUp_Action = ActionQual_Disabled +* configA.CtrEqCmpBDown_Action = ActionQual_Disabled +* void etpwmSetActionQualPwmA(etpwmREG1, configA) +* +* This function configures Action Qualifier submodule to generate PWMA +*/ +/* SourceId : ETPWM_SourceId_021 */ +/* DesignId : ETPWM_DesignId_021 */ +/* Requirements : HL_EPWM_SR13 */ +void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +{ + etpwm->AQCTLA = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) | + (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U)); + +} + +/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +* @brief Configure Action Qualifier submodule to generate PWMB +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param actionqualconfig Action Qualifier configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmActionQualConfig_t configB +* configB.CtrEqZero_Action = ActionQual_Set +* configB.CtrEqPeriod_Action = ActionQual_Disabled +* configB.CtrEqCmpAUp_Action = ActionQual_Disabled +* configB.CtrEqCmpADown_Action = ActionQual_Disabled +* configB.CtrEqCmpBUp_Action = ActionQual_Clear +* configB.CtrEqCmpBDown_Action = ActionQual_Disabled +* void etpwmSetActionQualPwmB(etpwmREG1, configB) +* +* This function configures Action Qualifier submodule to generate PWMB +*/ +/* SourceId : ETPWM_SourceId_022 */ +/* DesignId : ETPWM_DesignId_022 */ +/* Requirements : HL_EPWM_SR13 */ +void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t actionqualconfig) +{ + etpwm->AQCTLB = ((uint16)((uint16)actionqualconfig.CtrEqZero_Action << 0U) | + (uint16)((uint16)actionqualconfig.CtrEqPeriod_Action << 2U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpAUp_Action << 4U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpADown_Action << 6U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBUp_Action << 8U) | + (uint16)((uint16)actionqualconfig.CtrEqCmpBDown_Action << 10U)); + +} + +/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) +* @brief Enable DeadBand module +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param deadbandconfig DeadBand configuration +* +* This function configures Action Qualifier submodule to generate PWMB +*/ +/* SourceId : ETPWM_SourceId_023 */ +/* DesignId : ETPWM_DesignId_023 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) +{ + uint16 halfCycleMask = (uint16)((deadbandconfig.halfCycleEnable) ? 0x8000U : 0U); + etpwm->DBCTL = ((uint16)deadbandconfig.inputmode | + (uint16)deadbandconfig.outputmode | + (uint16)deadbandconfig.polarity | + halfCycleMask); +} + +/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm) +* @brief Disable DeadBand module +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function bypasses the Deadband submodule +*/ +/* SourceId : ETPWM_SourceId_024 */ +/* DesignId : ETPWM_DesignId_024 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmDisableDeadband(etpwmBASE_t *etpwm) +{ + etpwm->DBCTL = 0U; +} + +/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) +* @brief Sets the rising and falling edge delay +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param Rdelay 16-bit rising edge delay in terms of TCLK ticks +* @param Fdelay 16-bit falling edge delay in terms of TCLK ticks +* +* This function sets the rising and falling edge delays in the DeadBand submodule +*/ +/* SourceId : ETPWM_SourceId_025 */ +/* DesignId : ETPWM_DesignId_025 */ +/* Requirements : HL_EPWM_SR14 */ +void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) +{ + etpwm->DBRED = Rdelay; + etpwm->DBFED = Fdelay; +} + +/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) +* @brief Enable chopping +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param choppingconfig Chopper submodule configuration +* +* This function enables the chopper submodule with the given configuration +*/ +/* SourceId : ETPWM_SourceId_026 */ +/* DesignId : ETPWM_DesignId_026 */ +/* Requirements : HL_EPWM_SR15 */ +void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) +{ + etpwm->PCCTL = ((uint16)0x0001U | + (uint16)choppingconfig.oswdth | + (uint16)choppingconfig.freq | + (uint16)choppingconfig.duty); +} + +/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm) +* @brief Disable chopping +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables the chopper submodule +*/ +/* SourceId : ETPWM_SourceId_027 */ +/* DesignId : ETPWM_DesignId_027 */ +/* Requirements : HL_EPWM_SR15 */ +void etpwmDisableChopping(etpwmBASE_t *etpwm) +{ + etpwm->PCCTL = 0U; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +* @brief Select the tripzone zources +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param sources Trip zone sources (sources can be ORed) +* - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip source +* - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip source +* - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip source +* - OneShot_TZ1 : Enable TZ1 as a One-shot trip source +* - OneShot_TZ2 : Enable TZ2 as a One-shot trip source +* - OneShot_TZ3 : Enable TZ3 as a One-shot trip source +* - OneShot_TZ4 : Enable TZ4 as a One-shot trip source +* - OneShot_TZ5 : Enable TZ5 as a One-shot trip source +* - OneShot_TZ6 : Enable TZ6 as a One-shot trip source +* - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source +* - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source +* +* This function selects the tripzone sources for cycle-by-cycle and one-shot trip +*/ +/* SourceId : ETPWM_SourceId_028 */ +/* DesignId : ETPWM_DesignId_028 */ +/* Requirements : HL_EPWM_SR16 */ +void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +{ + etpwm->TZSEL |= sources; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +* @brief Disable the tripzone zources +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param sources Trip zone sources (sources can be ORed) +* - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip source +* - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip source +* - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip source +* - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip source +* - OneShot_TZ1 : Disable TZ1 as a One-shot trip source +* - OneShot_TZ2 : Disable TZ2 as a One-shot trip source +* - OneShot_TZ3 : Disable TZ3 as a One-shot trip source +* - OneShot_TZ4 : Disable TZ4 as a One-shot trip source +* - OneShot_TZ5 : Disable TZ5 as a One-shot trip source +* - OneShot_TZ6 : Disable TZ6 as a One-shot trip source +* - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source +* - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source +* +* This function disables the tripzone sources for cycle-by-cycle or one-shot trip +*/ +/* SourceId : ETPWM_SourceId_029 */ +/* DesignId : ETPWM_DesignId_029 */ +/* Requirements : HL_EPWM_SR16 */ +void etpwmDisableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) +{ + etpwm->TZSEL &= (uint16)~(uint16)sources; +} + +/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig) +* @brief Set the action for each trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param tripactionconfig Trip action configuration +* +* This function sets the action for each trip event +*/ +/* SourceId : ETPWM_SourceId_030 */ +/* DesignId : ETPWM_DesignId_030 */ +/* Requirements : HL_EPWM_SR17 */ +void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t tripactionconfig) +{ + etpwm->TZCTL = ((uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMA << 0U) | + (uint16)((uint16)tripactionconfig.TripEvent_ActionOnPWMB << 2U) | + (uint16)((uint16)tripactionconfig.DCAEVT1_ActionOnPWMA << 4U) | + (uint16)((uint16)tripactionconfig.DCAEVT2_ActionOnPWMA << 6U) | + (uint16)((uint16)tripactionconfig.DCBEVT1_ActionOnPWMB << 8U) | + (uint16)((uint16)tripactionconfig.DCBEVT2_ActionOnPWMB << 10U)); +} + +/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +* @brief Enables interrupt(EPWMx_TZINT) for the trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param interrupts Interrupts to be enabled (Interrupts can be ORed) +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function enables interrupt(EPWMx_TZINT) for the trip event +*/ +/* SourceId : ETPWM_SourceId_031 */ +/* DesignId : ETPWM_DesignId_031 */ +/* Requirements : HL_EPWM_SR18 */ +void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +{ + etpwm->TZEINT |= interrupts; +} + +/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +* @brief Disables interrupt(EPWMx_TZINT) for the trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed) +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function disables interrupt(EPWMx_TZINT) for the trip event +*/ +/* SourceId : ETPWM_SourceId_032 */ +/* DesignId : ETPWM_DesignId_032 */ +/* Requirements : HL_EPWM_SR18 */ +void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) +{ + etpwm->TZEINT &= (uint16)~(uint16)interrupts; +} + +/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) +* @brief Clears the trip event flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param trips Trip events +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function clears the trip event / Digital Compare output event flag +*/ +/* SourceId : ETPWM_SourceId_033 */ +/* DesignId : ETPWM_DesignId_033 */ +/* Requirements : HL_EPWM_SR19 */ +void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) +{ + etpwm->TZCLR = trips; +} + +/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) +* @brief Clears the trip interrupt flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function clears the trip interrupt flag +*/ +/* SourceId : ETPWM_SourceId_034 */ +/* DesignId : ETPWM_DesignId_034 */ +/* Requirements : HL_EPWM_SR19 */ +void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) +{ + etpwm->TZCLR = 1U; +} + +/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) +* @brief Force a trip event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param trip Trip events +* - CycleByCycleTrip +* - OneShotTrip +* - DCAEVT1_inter +* - DCAEVT2_inter +* - DCBEVT1_inter +* - DCBEVT2_inter +* +* This function forces a trip event / Digital Compare trip event via software +*/ +/* SourceId : ETPWM_SourceId_035 */ +/* DesignId : ETPWM_DesignId_035 */ +/* Requirements : HL_EPWM_SR20 */ +void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) +{ + etpwm->TZFRC = trip; +} + +/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ADC Start of Conversion A pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMxSOCA Selection Options +* - DCAEVT1 : DCAEVT1.soc event +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMxSOCA Period Select +* - EventPeriod_FirstEvent : Generate SOCA pulse on the first event +* - EventPeriod_SecondEvent : Generate SOCA pulse on the second event +* - EventPeriod_ThirdEvent : Generate SOCA pulse on the third event +* +* This function enables ADC Start of Conversion A pulse +*/ +/* SourceId : ETPWM_SourceId_036 */ +/* DesignId : ETPWM_DesignId_036 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0xF0FFU; + etpwm->ETSEL |= (uint16)((uint16)1U << 11U) | (uint16)((uint16)eventsource << 8U); + + etpwm->ETPS &= 0xF0FFU; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 8U); +} + +/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm) +* @brief Disable ADC Start of Conversion A pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables ADC Start of Conversion A pulse +*/ +/* SourceId : ETPWM_SourceId_037 */ +/* DesignId : ETPWM_DesignId_037 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmDisableSOCA(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0xF0FFU; +} + +/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ADC Start of Conversion B pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMxSOCB Selection Options +* - DCBEVT1 : DCBEVT1.soc event +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMxSOCB Period Select +* - EventPeriod_FirstEvent : Generate SOCB pulse on the first event +* - EventPeriod_SecondEvent : Generate SOCB pulse on the second event +* - EventPeriod_ThirdEvent : Generate SOCB pulse on the third event +* +* This function enables ADC Start of Conversion B pulse +*/ +/* SourceId : ETPWM_SourceId_038 */ +/* DesignId : ETPWM_DesignId_038 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0x0FFFU; + etpwm->ETSEL |= (uint16)((uint16)1U << 15U) | (uint16)((uint16)eventsource << 12U); + + etpwm->ETPS &= 0x0FFFU; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 12U); +} + +/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm) +* @brief Disable ADC Start of Conversion B pulse +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables ADC Start of Conversion B pulse +*/ +/* SourceId : ETPWM_SourceId_039 */ +/* DesignId : ETPWM_DesignId_039 */ +/* Requirements : HL_EPWM_SR21 */ +void etpwmDisableSOCB(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0x0FFFU; +} + +/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +* @brief Enable ePWM Interrupt +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param eventsource EPWMx_INT Selection Options +* - CTR_ZERO : Event CTR = Zero +* - CTR_PRD : Event CTR = PRD +* - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD +* - CTR_UP_CMPA : Event CTR = CMPA when the timer is incrementing +* - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is decrementing +* - CTR_UP_CMPB : Event CTR = CMPB when the timer is incrementing +* - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is decrementing +* @param eventperiod EPWMx_INT Period Select +* - EventPeriod_FirstEvent : Generate interrupt on the first event +* - EventPeriod_SecondEvent : Generate interrupt on the second event +* - EventPeriod_ThirdEvent : Generate interrupt on the third event +* +* This function enables EPWMx_INT generation +*/ +/* SourceId : ETPWM_SourceId_040 */ +/* DesignId : ETPWM_DesignId_040 */ +/* Requirements : HL_EPWM_SR22 */ +void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, etpwmEventPeriod_t eventperiod) +{ + etpwm->ETSEL &= 0xFFF0U; + etpwm->ETSEL |= (uint16)((uint16)1U << 3U) | (uint16)((uint16)eventsource << 0U); + + etpwm->ETPS &= 0xFFF0U; + etpwm->ETPS |= (uint16)((uint16)eventperiod << 0U); +} + +/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm) +* @brief Disable ePWM Interrupt +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* +* This function disables EPWMx_INT generation +*/ +/* SourceId : ETPWM_SourceId_041 */ +/* DesignId : ETPWM_DesignId_041 */ +/* Requirements : HL_EPWM_SR22 */ +void etpwmDisableInterrupt(etpwmBASE_t *etpwm) +{ + etpwm->ETSEL &= 0xFFF0U; +} + +/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) +* @brief Return event status flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @return event status flag +* Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag +* Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag +* Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag +* +* This function returns the event status flags +*/ +/* SourceId : ETPWM_SourceId_042 */ +/* DesignId : ETPWM_DesignId_042 */ +/* Requirements : HL_EPWM_SR23 */ +uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) +{ + return etpwm->ETFLG; +} + +/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) +* @brief Clear event status flag +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param events status flag (flags can be ORed) +* - Event_Interrupt +* - Event_SOCA +* - Event_SOCB +* +* This function clears the event status flags +*/ +/* SourceId : ETPWM_SourceId_043 */ +/* DesignId : ETPWM_DesignId_043 */ +/* Requirements : HL_EPWM_SR24 */ +void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) +{ + etpwm->ETCLR = events; +} + +/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) +* @brief Force an event +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @return events (events can be ORed) +* - Event_Interrupt +* - Event_SOCA +* - Event_SOCB +* +* This function forces an event +*/ +/* SourceId : ETPWM_SourceId_044 */ +/* DesignId : ETPWM_DesignId_044 */ +/* Requirements : HL_EPWM_SR25 */ +void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) +{ + etpwm->ETFRC = events; +} + +/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig) +* @brief Enable and configure digital compare events +* +* @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) +* @param digitalcompareconfig Digital Compare modue configuration +* +* Example usage (Removing semicolons to avoid MISRA warnings): +* etpwmDigitalCompareConfig_t config1 +* config1.DCAH_src = TZ1 +* config1.DCAL_src = TZ2 +* config1.DCBH_src = TZ1 +* config1.DCBL_src = TZ3 +* config1.DCAEVT1_event = DCAH_High +* config1.DCAEVT2_event = DCAL_High +* config1.DCBEVT1_event = DCBL_High +* config1.DCBEVT2_event = DCBL_High_DCBH_low +* etpwmEnableDigitalCompareEvents(etpwmREG1, config1) +* +* This function enbales and configures the digital compare events. HTis function can also be used to disable digital compare events +*/ +/* SourceId : ETPWM_SourceId_045 */ +/* DesignId : ETPWM_DesignId_045 */ +/* Requirements : HL_EPWM_SR26 */ +void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, etpwmDigitalCompareConfig_t digitalcompareconfig) +{ + etpwm->DCTRIPSEL = ((uint16)((uint16)digitalcompareconfig.DCAH_src << 0U) | + (uint16)((uint16)digitalcompareconfig.DCAL_src << 4U) | + (uint16)((uint16)digitalcompareconfig.DCBH_src << 8U) | + (uint16)((uint16)digitalcompareconfig.DCBL_src << 12U)); + + etpwm->TZDCSEL = ((uint16)((uint16)digitalcompareconfig.DCAEVT1_event << 0U) | + (uint16)((uint16)digitalcompareconfig.DCAEVT2_event << 3U) | + (uint16)((uint16)digitalcompareconfig.DCBEVT1_event << 6U) | + (uint16)((uint16)digitalcompareconfig.DCBEVT2_event << 9U)); +} + +/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_046 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG1->CMPA; + config_reg->CONFIG_CMPB = etpwmREG1->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG1->DBRED; + config_reg->CONFIG_DBFED = etpwmREG1->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG1->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT; + } +} + +/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_47 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG2->CMPA; + config_reg->CONFIG_CMPB = etpwmREG2->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG2->DBRED; + config_reg->CONFIG_DBFED = etpwmREG2->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG2->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT; + } +} + +/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_048 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG3->CMPA; + config_reg->CONFIG_CMPB = etpwmREG3->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG3->DBRED; + config_reg->CONFIG_DBFED = etpwmREG3->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG3->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT; + } +} + +/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_049 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG4->CMPA; + config_reg->CONFIG_CMPB = etpwmREG4->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG4->DBRED; + config_reg->CONFIG_DBFED = etpwmREG4->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG4->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT; + } +} + +/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_050 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR3232 */ +void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG5->CMPA; + config_reg->CONFIG_CMPB = etpwmREG5->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG5->DBRED; + config_reg->CONFIG_DBFED = etpwmREG5->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG5->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT; + } +} + +/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_051 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG6->CMPA; + config_reg->CONFIG_CMPB = etpwmREG6->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG6->DBRED; + config_reg->CONFIG_DBFED = etpwmREG6->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG6->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT; + } +} + +/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : ETPWM_SourceId_052 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : HL_EPWM_SR32 */ +void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG7->CMPA; + config_reg->CONFIG_CMPB = etpwmREG7->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG7->DBRED; + config_reg->CONFIG_DBFED = etpwmREG7->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG7->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT; + } +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ Index: firmware/source/mdio.c =================================================================== diff -u --- firmware/source/mdio.c (revision 0) +++ firmware/source/mdio.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,246 @@ +/** + * \file mdio.c + * + * \brief MDIO APIs. + * + * This file contains the device abstraction layer APIs for MDIO. + */ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "hw_reg_access.h" +#include "mdio.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* +* INTERNAL MACRO DEFINITIONS +*******************************************************************************/ +#define PHY_REG_MASK (0x1FU) +#define PHY_ADDR_MASK (0x1FU) +#define PHY_DATA_MASK (0xFFFFU) +#define PHY_REG_SHIFT (21U) +#define PHY_ADDR_SHIFT (16U) + +/******************************************************************************* +* API FUNCTION DEFINITIONS +*******************************************************************************/ + +/** + * \brief Reads a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param dataPtr Pointer where the read value shall be written. + * + * \return status of the read \n + * TRUE - read is successful.\n + * FALSE - read is not acknowledged properly. + * + **/ +/* SourceId : ETH_SourceId_059 */ +/* DesignId : ETH_DesignId_059*/ +/* Requirements : HL_ETH_SR41, HL_ETH_SR45 */ +boolean MDIOPhyRegRead(uint32 baseAddr, uint32 phyAddr, + uint32 regNum, volatile uint16 * dataPtr) +{ + boolean retVal = FALSE; + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO) + { + } /* Wait */ + + HWREG(baseAddr + MDIO_USERACCESS0) + = (((uint32)MDIO_USERACCESS0_READ) | MDIO_USERACCESS0_GO + |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT) + |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT)); + + /* wait for command completion */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO) + { + } /* Wait */ + + /* Store the data if the read is acknowledged */ + if(((HWREG(baseAddr + MDIO_USERACCESS0)) & MDIO_USERACCESS0_ACK) == MDIO_USERACCESS0_ACK) + { + /*SAFETYMCUSW 439 S MR:11.3 "Output is a 16 bit Value to be stored - Advisory as per MISRA" */ + *dataPtr = (uint16)((HWREG(baseAddr + MDIO_USERACCESS0)) + & PHY_DATA_MASK); + retVal = TRUE; + } + + return retVal; +} + +/** + * \brief Writes a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param RegVal Value to be written. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_058 */ +/* DesignId : ETH_DesignId_058*/ +/* Requirements : HL_ETH_SR41 */ +void MDIOPhyRegWrite(uint32 baseAddr, uint32 phyAddr, + uint32 regNum, uint16 RegVal) +{ + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO) + { + } /* Wait */ + + HWREG(baseAddr + MDIO_USERACCESS0) + = (MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO + |((regNum & PHY_REG_MASK) << PHY_REG_SHIFT) + |((phyAddr & PHY_ADDR_MASK) << PHY_ADDR_SHIFT) + | RegVal); + + /* wait for command completion*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO) == MDIO_USERACCESS0_GO) + { + } /* Wait */ +} +/** + * \brief Reads the alive status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * is alive. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO alive register state + * + **/ +/* SourceId : ETH_SourceId_062 */ +/* DesignId : ETH_DesignId_062*/ +/* Requirements : HL_ETH_SR42 */ +uint32 MDIOPhyAliveStatusGet(uint32 baseAddr) +{ + return (HWREG(baseAddr + MDIO_ALIVE)); +} + +/** + * \brief Reads the link status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * link is active. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO link register state + * + **/ +/* SourceId : ETH_SourceId_061 */ +/* DesignId : ETH_DesignId_061*/ +/* Requirements : HL_ETH_SR42 */ +uint32 MDIOPhyLinkStatusGet(uint32 baseAddr) +{ + return (HWREG(baseAddr + MDIO_LINK)); +} + +/** + * \brief Initializes the MDIO peripheral. This enables the MDIO state + * machine, uses standard pre-amble and set the clock divider value. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param mdioInputFreq The clock input to the MDIO module + * \param mdioOutputFreq The clock output required on the MDIO bus + * \return None + * + **/ +/* SourceId : ETH_SourceId_060 */ +/* DesignId : ETH_DesignId_060*/ +/* Requirements : HL_ETH_SR39 */ +void MDIOInit(uint32 baseAddr, uint32 mdioInputFreq, + uint32 mdioOutputFreq) +{ + uint32 clkDiv = (mdioInputFreq/mdioOutputFreq) - 1U; + HWREG(baseAddr + MDIO_CONTROL) = ((clkDiv & MDIO_CONTROL_CLKDIV) + | MDIO_CONTROL_ENABLE + | MDIO_CONTROL_PREAMBLE + | MDIO_CONTROL_FAULTENB); +} + +/** + * \brief Function to enable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : HL_ETH_SR40 */ +void MDIOEnable(uint32 baseAddr) { + HWREG(baseAddr + MDIO_CONTROL) = HWREG(baseAddr + MDIO_CONTROL) + | MDIO_CONTROL_ENABLE; +} + +/** + * \brief Function to disable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_057 */ +/* DesignId : ETH_DesignId_057*/ +/* Requirements : HL_ETH_SR40 */ +void MDIODisable(uint32 baseAddr) { + HWREG(baseAddr + MDIO_CONTROL) = HWREG(baseAddr + MDIO_CONTROL) + & (~MDIO_CONTROL_ENABLE); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ Index: firmware/source/phy_dp83640.c =================================================================== diff -u --- firmware/source/phy_dp83640.c (revision 0) +++ firmware/source/phy_dp83640.c (revision dd790ad31a95776e2f3d72fc8eac786f956ab945) @@ -0,0 +1,431 @@ +/** + * \file phy_dp83640.c + * + * \brief APIs for configuring DP83640. + * + * This file contains the device abstraction APIs for PHY DP83640. + */ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* +* API FUNCTION DEFINITIONS +*******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : HL_ETH_SR49 */ +uint32 Dp83640IDGet(uint32 mdioBaseAddr, uint32 phyAddr) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_ID1, &data); + + /* update the ID1 value */ + id = (uint32)data; + id = (uint32)((uint32)id << PHY_ID_SHIFT); + + /* read the ID2 register */ + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_ID2, &data); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : HL_ETH_SR47 */ +boolean Dp83640LinkStatusGet(uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while (retVal == TRUE) + { + /* First read the BSR of the PHY */ + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BSR, &linkStatus); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if((linkStatus & PHY_LINK_STATUS) != 0U) + { + /* Check if MDIO LINK register is updated */ + linkStatus = (uint16)MDIOPhyLinkStatusGet(mdioBaseAddr); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if((linkStatus & (uint16)((uint16)1U << phyAddr)) != 0U) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if(retries != 0U) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if(retries != 0U) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * DP83640_100BTX - 100BaseTX + * DP83640_100BTX_FD - Full duplex capabilty for 100BaseTX + * DP83640_10BT - 10BaseT + * DP83640_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : HL_ETH_SR46 */ +boolean Dp83640AutoNegotiate(uint32 mdioBaseAddr, + uint32 phyAddr, uint16 advVal) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, &data) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, data); + + if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, &data) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_AUTONEG_ADV, &anar); + anar &= (uint16)(~0xff10U); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, (uint32)PHY_AUTONEG_ADV, (anar |advVal)); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, data); + + /* Get the auto negotiation status*/ + if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BSR, &data) != TRUE) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while((((uint16)(PHY_AUTONEG_INCOMPLETE)) == (data & (uint16)(PHY_AUTONEG_STATUS))) && (retVal == TRUE) && (phyNegTries > 0U)) + { + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BSR, &data); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if((data & PHY_AUTONEG_ABLE) != 0U) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : HL_ETH_SR48 */ +boolean Dp83640PartnerAbilityGet(uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 *ptnerAblty) +{ + return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, + ptnerAblty)); +} + + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : HL_ETH_SR44 */ +void Dp83640Reset(uint32 mdioBaseAddr, uint32 phyAddr) +{ + uint16 regVal = 0U; + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET); + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, ®Val); + + /* : This bit is self-clearing and returns 1 until the reset process is complete. */ + while((regVal & PHY_SOFTRESET) != 0U) + { + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, ®Val); + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : HL_ETH_SR51 */ +void Dp83640EnableLoopback(uint32 mdioBaseAddr, uint32 phyAddr) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, ®Val); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= (uint16)(~((uint16)PHY_AUTONEG_ENABLE)); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, regVal); + + while(delay > 0U) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : HL_ETH_SR51 */ +void Dp83640DisableLoopback(uint32 mdioBaseAddr, uint32 phyAddr) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, ®Val); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= (uint16)(~((uint16)PHY_LPBK_ENABLE)); + + MDIOPhyRegWrite(mdioBaseAddr, phyAddr, (uint32)PHY_BCR, regVal); + + while(delay > 0U) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following order: + * Timestamp_ns [63:49] + * Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : HL_ETH_SR53 */ +uint64 Dp83640GetTimeStamp(uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker (due to use of & ?) */ + uint16 *tsptr = &ts; + uint64 timeStamp = 0u; + if(type == 1U) + { + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_TXTS, tsptr); + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_TXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_TXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_TXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + } + else + { + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_RXTS, tsptr); + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_RXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_RXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + (void)MDIOPhyRegRead(mdioBaseAddr, phyAddr, (uint32)PHY_RXTS, tsptr); + timeStamp = timeStamp << 16U ; + timeStamp |= (uint64)ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Dp83640PartnerSpdGet(uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 *ptnerAblty) +{ + return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, + ptnerAblty)); +} +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**************************** End Of File ***********************************/