Index: Integrity.c
===================================================================
diff -u -rfe57ea76fe86046ecef536ba0d144af8d3399e15 -r310b61154f321481bed8638cad8117b336d76a29
--- Integrity.c	(.../Integrity.c)	(revision fe57ea76fe86046ecef536ba0d144af8d3399e15)
+++ Integrity.c	(.../Integrity.c)	(revision 310b61154f321481bed8638cad8117b336d76a29)
@@ -46,14 +46,12 @@
 static U32 currentProcessedSize;                                ///< Current data size processed for CRC calculation.
 static U32 crcCalculated;                                       ///< The calculated CRC value.
 static SELF_TEST_STATUS_T integrityTestStatus;                  ///< Current firmware integrity test status.
-static U32 processorRAMStatusCounter = 0;                       ///< Counter use to log system event if processor RAM error is detected.  DN-02SEPT2022
-static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal single bit RAM error.       - DN-02SEPT2022
+static U32 processorRAMStatusCounter = 0;                       ///< Counter used to check processor RAM error.  - DN-01SEPT2022
+static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal the processor RAM error. - DN-01SEPT2022
+/// Time threshold to check RAM error is 2 seconds
+static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);    // DN-02SEPT2022
 
 
-/// Time threshold to check RAM error is 1 second
-static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((1 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);    // DN-02SEPT2022
-
-
 /*********************************************************************//**
  * @brief
  * The initIntegrity function initializes the Integrity module.
@@ -84,10 +82,13 @@
     // Check for processor RAM error
     if ( ++processorRAMStatusCounter > RAM_ERROR_CHECK_TIME_THRESHOLD )
     {
-        tcram1ErrStat = tcram1REG->RAMERRSTATUS;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
-        tcram2ErrStat = tcram2REG->RAMERRSTATUS;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
-        err1 = tcram1ErrStat & SERR;
-        err2 = tcram2ErrStat & SERR;
+        tcram1ErrStat = tcram1REG->RAMERRSTATUS;    // B0TCM in TCRAM Module Error Status Register
+        tcram2ErrStat = tcram2REG->RAMERRSTATUS;    // B1TCM in TCRAM Module Error Status Register
+        err1 = tcram1ErrStat & SERR;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
+        err2 = tcram2ErrStat & SERR;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
+
+        err1 = SERR; err2 = SERR;   // Force values for testing only - DN-06SEPT2022
+
         if( ( err1 != 0 ) || ( err2 != 0 ) )
         {
             if ( FALSE == singleBitRAMErrorFlag )
@@ -96,16 +97,16 @@
               SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, 0, 0 );
               singleBitRAMErrorFlag = TRUE;
             }
-            tcram1ErrStat = tcram1ErrStat & 0xFFFFFFFE;     // Clear bit 0
-            tcram2ErrStat = tcram2ErrStat & 0xFFFFFFFE;     // Clear bit 0
         }
 
+        tcram1ErrStat = ADDR_DEC_FAIL; tcram2ErrStat = DERR;   // Force values for testing only - DN-06SEPT2022
+
         err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
         err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
 
         if ( ( err1 != 0 ) || ( err2 != 0 ) )
         {
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );     // Commented out for debug only - DN-07SEPT2022
         }
 
         processorRAMStatusCounter = 0;