Index: RTC.c =================================================================== diff -u -r1b53e0ea50bed8f2155aec6e9c888a4b776b0edc -r8ba5809ebcb21ab17250a9aa983b8b01c80c1dbe --- RTC.c (.../RTC.c) (revision 1b53e0ea50bed8f2155aec6e9c888a4b776b0edc) +++ RTC.c (.../RTC.c) (revision 8ba5809ebcb21ab17250a9aa983b8b01c80c1dbe) @@ -176,7 +176,6 @@ static U32 RAMBufferLength = 0; static U32 lastEpochTime = 0; // Last value that has been converted to epoch static U32 previousTransferLength = 0; -static U32 RTCPublishIntervalCounter = 1; static U32 timeCounter = 1; static U32 numberOfFailedRTCTransfers = 1; @@ -896,14 +895,14 @@ | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIFT_10 ) /* enable WDELAY */ | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT_11 ) /* lock transmission */ | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU ); /* chip select */ i++; } mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT_13 ) /* buffer mode */ | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT_12 ) /* chip select hold */ | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIFT_10 ) /* enable WDELAY */ | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU ); /* chip select */ transferStatus = TRUE; } @@ -989,7 +988,7 @@ { result = RTC_EXEC_STATE_PREP_RAM; } - else if ( (timeCounter == TIMER_COUNTER_TO_REQUEST_READ) ) + else if ( timeCounter == TIMER_COUNTER_TO_REQUEST_READ ) { prepBufferForReadCommand( RTC_GENERAL_BUFFER_LENGTH ); result = RTC_EXEC_STATE_READ;