Index: firmware/App/HDCommon.h =================================================================== diff -u -rfd12aa494e60cc32852a32d1c3aa2b49eb013fdf -ra5b2f7f58ed39bd84d2ba6986850cae7feddfeb4 --- firmware/App/HDCommon.h (.../HDCommon.h) (revision fd12aa494e60cc32852a32d1c3aa2b49eb013fdf) +++ firmware/App/HDCommon.h (.../HDCommon.h) (revision a5b2f7f58ed39bd84d2ba6986850cae7feddfeb4) @@ -30,28 +30,28 @@ // ********** development build switches ********** #ifndef _RELEASE_ -#define UF_TEST_ENABLED 1 // ultrafiltration test build (hard codes treatment params, re-purposes off/stop buttons) -#define UF_TEST_WITH_DG 1 // ultrafiltration test build (sets up DG in standby mode) +//#define UF_TEST_ENABLED 1 // ultrafiltration test build (hard codes treatment params, re-purposes off/stop buttons) +//#define UF_TEST_WITH_DG 1 // ultrafiltration test build (sets up DG in standby mode) #ifndef _VECTORCAST_ - #define DISABLE_UI_TREATMENT_WORKFLOW 1 // disable UI treatment workflow +// #define DISABLE_UI_TREATMENT_WORKFLOW 1 // disable UI treatment workflow // #define RM46_EVAL_BOARD_TARGET 1 // limited build runs on RM46 eval board // #define BREADBOARD_TARGET 1 // old breadboard system build - no longer used? // #define SIMULATE_UI 1 // build w/o requirement that UI be there // #define TASK_TIMING_OUTPUT_ENABLED 1 // re-purposes alarm lamp pins for task timing #define SKIP_POST 1 // skip POST tests - all pass // #define LIMITED_NVDATA_CRC_CHECKS 1 // only perform POST CRC checks on nv-data records that are implemented so far - #define DISABLE_3WAY_VALVES 1 // disable 3-way valves - #define TST_3WAY_VALVES_ALWAYS_OPEN 1 // after POST and homing, open all 4 valves +// #define DISABLE_3WAY_VALVES 1 // disable 3-way valves +// #define TST_3WAY_VALVES_ALWAYS_OPEN 1 // after POST and homing, open all 4 valves #define DISABLE_ACCELS 1 // disable accelerometer POST and monitoring #define DISABLE_CRC_ERROR 1 // do not error on bad CRC for CAN messages #define DISABLE_ACK_ERRORS 1 // do not error on failure of other node(s) to ACK a message -// #define DISABLE_MOTOR_CURRENT_CHECKS 1 // do not error on HD pump current checks -// #define DISABLE_PUMP_FLOW_CHECKS 1 // do not error on HD pump flow checks -// #define DISABLE_PUMP_SPEED_CHECKS 1 // do not error on HD pump speed checks -// #define DISABLE_PUMP_DIRECTION_CHECKS 1 // do not error on HD pump direction checks -// #define DISABLE_PRESSURE_CHECKS 1 // do not error on HD pressure checks + #define DISABLE_MOTOR_CURRENT_CHECKS 1 // do not error on HD pump current checks + #define DISABLE_PUMP_FLOW_CHECKS 1 // do not error on HD pump flow checks + #define DISABLE_PUMP_SPEED_CHECKS 1 // do not error on HD pump speed checks + #define DISABLE_PUMP_DIRECTION_CHECKS 1 // do not error on HD pump direction checks + #define DISABLE_PRESSURE_CHECKS 1 // do not error on HD pressure checks #define DISABLE_UF_ALARMS 1 // do not error on HD ultrafiltration checks -// #define RUN_PUMPS_OPEN_LOOP 1 // BP and DPi pumps will be run open loop (no flow sensor feedback) + #define RUN_PUMPS_OPEN_LOOP 1 // BP and DPi pumps will be run open loop (no flow sensor feedback) // #define RAW_FLOW_SENSOR_DATA 1 // test build will not filter flow sensor data // #define READ_FPGA_ASYNC_DATA 1 // test build reads non-priority register page every other time // #define FLOW_DEBUG 1 // test build sends flow, signal strength, and occlusion readings to debug UART