Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r620104f4a9e3148575703981a3063b9605b6e9b8 -r1bbf9da32e622975efed00b1a7589387a9829440
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 620104f4a9e3148575703981a3063b9605b6e9b8)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 1bbf9da32e622975efed00b1a7589387a9829440)
@@ -121,10 +121,10 @@
 static BOOL fpgaReadCommandResponseReceived = FALSE;
 
 // FPGA comm buffers
-static U08 fpgaWriteCmdBuffer[FPGA_WRITE_CMD_BUFFER_LEN];
-static U08 fpgaReadCmdBuffer[FPGA_READ_CMD_BUFFER_LEN];
-static U08 fpgaWriteResponseBuffer[FPGA_WRITE_RSP_BUFFER_LEN];
-static U08 fpgaReadResponseBuffer[FPGA_READ_RSP_BUFFER_LEN];
+static U08 fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_BUFFER_LEN ];
+static U08 fpgaReadCmdBuffer[ FPGA_READ_CMD_BUFFER_LEN ];
+static U08 fpgaWriteResponseBuffer[ FPGA_WRITE_RSP_BUFFER_LEN ];
+static U08 fpgaReadResponseBuffer[ FPGA_READ_RSP_BUFFER_LEN ];
 
 // DMA control records
 static g_dmaCTRL fpgaDMAWriteControlRecord;
@@ -450,13 +450,13 @@
     U16 crc;
 
     // construct read command to read 3 registers starting at address 0
-    fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE;
-    fpgaReadCmdBuffer[1] = 0x00;    // start at FPGA address 0
-    fpgaReadCmdBuffer[2] = 0x00;
-    fpgaReadCmdBuffer[3] = sizeof(FPGA_HEADER_T);
+    fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
+    fpgaReadCmdBuffer[ 1 ] = 0x00;    // start at FPGA address 0
+    fpgaReadCmdBuffer[ 2 ] = 0x00;
+    fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_HEADER_T);
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
-    fpgaReadCmdBuffer[4] = GET_MSB_OF_WORD( crc );
-    fpgaReadCmdBuffer[5] = GET_LSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
     // prep DMA for sending the read cmd and receiving the response
     fpgaReadCommandInProgress = TRUE;
     setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T) + FPGA_CRC_LEN );
@@ -485,18 +485,18 @@
     if ( TRUE == fpgaReadCommandResponseReceived )
     {
         // did FPGA Ack the read command?
-        if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK )
+        if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
         {
             U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T);
             U32 crcPos = rspSize;
-            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos], fpgaReadResponseBuffer[crcPos + 1] );
+            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
 
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[FPGA_READ_RSP_HDR_LEN], sizeof(FPGA_HEADER_T) );
+                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else
@@ -536,28 +536,28 @@
     U16 crc;
 
     // construct bulk write command to write actuator data registers starting at address 3  (TODO - change address later)
-    fpgaWriteCmdBuffer[0] = FPGA_WRITE_CMD_CODE;
-    fpgaWriteCmdBuffer[1] = 0x08;    // start at FPGA address 8
-    fpgaWriteCmdBuffer[2] = 0x00;
-    fpgaWriteCmdBuffer[3] = sizeof(FPGA_ACTUATORS_T);
-    memcpy( &(fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN]), &fpgaActuatorSetPoints, sizeof(FPGA_ACTUATORS_T) );
-    crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN+sizeof(FPGA_ACTUATORS_T) );
-    fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+sizeof(FPGA_ACTUATORS_T)] = GET_MSB_OF_WORD( crc );
-    fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+sizeof(FPGA_ACTUATORS_T) + 1] = GET_LSB_OF_WORD( crc );
+    fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE;
+    fpgaWriteCmdBuffer[ 1 ] = 0x08;    // start at FPGA address 8
+    fpgaWriteCmdBuffer[ 2 ] = 0x00;
+    fpgaWriteCmdBuffer[ 3 ] = sizeof(FPGA_ACTUATORS_T);
+    memcpy( &( fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ] ), &fpgaActuatorSetPoints, sizeof( FPGA_ACTUATORS_T ) );
+    crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) );
+    fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) ] = GET_MSB_OF_WORD( crc );
+    fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + 1 ] = GET_LSB_OF_WORD( crc );
     // construct bulk read command to read sensor data registers starting at address 8
-    fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE;
-    fpgaReadCmdBuffer[1] = 0x08;    // start at FPGA address 0x108 (264)
-    fpgaReadCmdBuffer[2] = 0x01;
-    fpgaReadCmdBuffer[3] = sizeof(FPGA_SENSORS_T);
+    fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
+    fpgaReadCmdBuffer[ 1 ] = 0x08;    // start at FPGA address 0x108 (264)
+    fpgaReadCmdBuffer[ 2 ] = 0x01;
+    fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_SENSORS_T);
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
-    fpgaReadCmdBuffer[4] = GET_MSB_OF_WORD( crc );
-    fpgaReadCmdBuffer[5] = GET_LSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
     // prep DMA for sending the bulk write cmd and receiving its response
-    setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + sizeof(FPGA_ACTUATORS_T) + FPGA_CRC_LEN );
+    setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + FPGA_CRC_LEN );
     setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN + FPGA_CRC_LEN );
     // prep DMA for sending the bulk read cmd and receiving its response
     setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN );
-    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T) + FPGA_CRC_LEN );
+    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof( FPGA_SENSORS_T ) + FPGA_CRC_LEN );
     // set fpga comm flags for bulk write cmd and follow-up bulk read command
     fpgaWriteCommandInProgress = TRUE;
     fpgaBulkWriteAndReadInProgress = TRUE;
@@ -583,7 +583,7 @@
     FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS;
 
     // check bulk write command success
-    if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[0] != FPGA_WRITE_CMD_ACK ) )
+    if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[ 0 ] != FPGA_WRITE_CMD_ACK ) )
     {
         fpgaCommRetryCount++;
     }
@@ -592,18 +592,18 @@
     if ( TRUE == fpgaReadCommandResponseReceived )
     {
         // did FPGA Ack the read command?
-        if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK )
+        if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
         {
             U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T);
             U32 crcPos = rspSize;
-            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos], fpgaReadResponseBuffer[crcPos + 1] );
+            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
 
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[FPGA_READ_RSP_HDR_LEN], sizeof(FPGA_SENSORS_T) );
+                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_SENSORS_T ) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else // bad CRC