Index: firmware/App/Services/SystemComm.c
===================================================================
diff -u -r22dba2a64a6d8251e909e6f964d74983486856a9 -r850950d51f589845f157aa6e883b8c7588479c9d
--- firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision 22dba2a64a6d8251e909e6f964d74983486856a9)
+++ firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision 850950d51f589845f157aa6e883b8c7588479c9d)
@@ -57,10 +57,8 @@
 #define MSG_NOT_ACKED_MAX_RETRIES       3       ///< Maximum number of times a message that requires ACK that was not ACK'd can be re-sent before alarm
 #define PENDING_ACK_LIST_SIZE           25      ///< Maximum number of Denali messages that can be pending ACK at any given time
 
-#define MAX_FPGA_CLOCK_SPEED_ERRORS     1   //3       ///< maximum number of FPGA clock speed errors within window period before alarm - // Force 1 for testing ONLY. TODO: will use value 3.  DN-19SEPT2022
-//#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS    (10 * SEC_PER_MIN * MS_PER_SECOND)    ///< FPGA clock speed error window - // DN-16SEPT2022
-//#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS    (1 * SEC_PER_MIN * MS_PER_SECOND)    ///< FPGA clock speed error window - // For 1 minute for testing ONLY. DN-19SEPT2022
-#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS    (1 * MS_PER_SECOND)    ///< FPGA clock speed error window - // Force 1 second for testing ONLY. DN-19SEPT2022
+#define MAX_FPGA_CLOCK_SPEED_ERRORS     3       ///< maximum number of FPGA clock speed errors within window period before alarm
+#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS    (10 * SEC_PER_MIN * MS_PER_SECOND)    ///< FPGA clock speed error window
 
 #pragma pack(push, 1)
 
@@ -154,8 +152,8 @@
     // Initialize bad message CRC time windowed count
     initTimeWindowedCount( TIME_WINDOWED_COUNT_BAD_MSG_CRC, MAX_COMM_CRC_FAILURES, MAX_COMM_CRC_FAILURE_WINDOW_MS );
 
-    // initialize FPGA clock speed error time windowed count
-    initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR, MAX_FPGA_CLOCK_SPEED_ERRORS, MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS);   // DN-16SEPT2022
+    // Initialize FPGA clock speed error time windowed count
+    initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR, MAX_FPGA_CLOCK_SPEED_ERRORS, MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS);
 
     // Initialize pending ACK list
     for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ )