Index: firmware/source/sys_link.cmd =================================================================== diff -u -rccce21ad66b7806e1ef1484050b841e66e69afd2 -rd2dfbe0338029375e84218c3f090f1971d9878ae --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision ccce21ad66b7806e1ef1484050b841e66e69afd2) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision d2dfbe0338029375e84218c3f090f1971d9878ae) @@ -1,36 +1,36 @@ /*----------------------------------------------------------------------------*/ /* sys_link.cmd */ /* */ -/* -* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions * are met: * -* Redistributions of source code must retain the above copyright +* Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ @@ -56,8 +56,8 @@ MEMORY { - VECTORS (X) : origin=0x00010020 length=0x00000020 //APP_START_ADDRESS = 0x10020 - FLASH0 (RX) : origin=0x00010040 length=0x0012FFC0 + VECTORS (X) : origin=0x00000000 length=0x00000020 + FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 STACKS (RW) : origin=0x08000000 length=0x00005800 RAM (RW) : origin=0x08005800 length=0x0002a800 @@ -67,18 +67,49 @@ #if 1 MEMORY { - VECTORS (X) : origin=0x00014000 length=0x00000020 - CRCMEM (RX) : origin=0x00014020 length=0x000001E0 - FLASH0 (RX) : origin=0x00014200 length=0x0012BDFF - STACKS (RW) : origin=0x08000000 length=0x00004c00 - RAM (RW) : origin=0x08006c00 length=0x00029400 + VECTORS (X) : origin=0x00010020 + length=0x00000020 + vfill = 0xffffffff + CRCMEM (RX) : origin=end(VECTORS) + length=0x000001E0 + vfill = 0xffffffff + + FLASH0 (RX) : origin=end(CRCMEM) + length=(0x0013FFFF - end(CRCMEM)) + vfill = 0xffffffff + + STACKS (RW) : origin=0x08000000 + length=0x00004c00 + + RAM (RW) : origin=0x08004c00 + length=0x0002b400 #endif +#if 1 + ECC_VEC (R) : origin=(0xf0400000 + (start(VECTORS) >> 3)) + length=(size(VECTORS) >> 3) + ECC={algorithm=algoL2R4F021, input_range=VECTORS} + + ECC_CRC (R) : origin=(0xf0400000 + (start(CRCMEM) >> 3)) + length=(size(CRCMEM) >> 3) + ECC={algorithm=algoL2R4F021, input_range=CRCMEM } + + ECC_FLA0 (R) : origin=(0xf0400000 + (start(FLASH0) >> 3)) + length=(size(FLASH0) >> 3) + ECC={algorithm=algoL2R4F021, input_range=FLASH0 } +#endif /* USER CODE END */ } /* USER CODE BEGIN (3) */ /* IGNORE the generated Sections code, overridden below */ +ECC +{ + algoL2R4F021 : address_mask = 0xfffffff8 /* Address Bits 31:3 */ + hamming_mask = R4 /* Use R4/R5 build in Mask */ + parity_mask = 0x0c /* Set which ECC bits are Even and Odd parity */ + mirroring = F021 /* RM57Lx and TMS570LCx are build in F021 */ +} #if 0 /* USER CODE END */ @@ -88,26 +119,26 @@ SECTIONS { .intvecs : {} > VECTORS - .text : {} > FLASH0 - .const : {} > FLASH0 - .cinit : {} > FLASH0 - .pinit : {} > FLASH0 + .text : {} > FLASH0 + .const : {} > FLASH0 + .cinit : {} > FLASH0 + .pinit : {} > FLASH0 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM + - /* USER CODE BEGIN (4) */ #endif /* Override Sections with CRCs here */ #if 1 SECTIONS { .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C ) - .text : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .const : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .cinit : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) - .pinit : {} > FLASH0 + .text align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .const align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .cinit align(32) : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .pinit align(32) : {} > FLASH0 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM