Index: firmware/App/Common.h =================================================================== diff -u -ra635fc9674913460c74831add7886c85d8aaf8f1 -r53165945d15dd7a30b3d194573507cbd31e5314f --- firmware/App/Common.h (.../Common.h) (revision a635fc9674913460c74831add7886c85d8aaf8f1) +++ firmware/App/Common.h (.../Common.h) (revision 53165945d15dd7a30b3d194573507cbd31e5314f) @@ -84,7 +84,13 @@ #define MASK_OFF_LSW 0xFFFF0000 #define SHIFT_8_BITS_FOR_BYTE_SHIFT 8 #define SHIFT_16_BITS_FOR_WORD_SHIFT 16 +#define MASK_OFF_NIBBLE_LSB 0xF0 +#define MASK_OFF_NIBBLE_MSB 0x0F +#define MAX_DOUBLE_DIGIT_DECIMAL 99U +#define MAX_SINGLE_DIGIT_DECIMAL 9U +#define SHIFT_BITS_BY_4 4U + // **** Common Macros **** #define CAP(v,u) ((v) > (u) ? (u) : (v)) Index: firmware/App/Controllers/RTC.c =================================================================== diff -u -rca4b67841f4c9136401a2f1011668eb0a468f19a -r53165945d15dd7a30b3d194573507cbd31e5314f --- firmware/App/Controllers/RTC.c (.../RTC.c) (revision ca4b67841f4c9136401a2f1011668eb0a468f19a) +++ firmware/App/Controllers/RTC.c (.../RTC.c) (revision 53165945d15dd7a30b3d194573507cbd31e5314f) @@ -20,82 +20,89 @@ #include "RTC.h" #include "mibspi.h" +// TODO: TRANSFER SOME OF THE DEFINES TO COMMON.H // ********** Definitions ********** -#define RTC_REG_1_12_HOUR_MODE 0X0004 // 12-hour or 24-hour mode -#define RTC_REG_1_PORO 0X0008 // Power On Reset Override -#define RTC_REG_1_CLK_STOPPED 0X0020 // RTC source clock -#define RTC_REG_1_UNUSED 0X0040 // Unused -#define RTC_REG_1_EXT_CLK_MODE 0X0080 // RTC external or normal mode +#define RTC_REG_1_12_HOUR_MODE_MASK 0x0004 // 12-hour mode mask +#define RTC_REG_1_PORO 0x0008 // Power On Reset Override +#define RTC_REG_1_CLK_STOPPED_MASK 0x0020 // RTC source clock mask +#define RTC_REG_1_UNUSED_MASK 0x0040 // Unused mask +#define RTC_REG_1_EXT_CLK_MODE_MASK 0x0080 // RTC external clock test mode mask -#define RTC_REG_2_MASK 0X00FF -#define RTC_REG_2_MSF 0X0080 // Minute or second interrupt -#define RTC_REG_2_CDTF 0X0008 // Countdown timer interrupt -#define RTC_REG_2_AF 0X0010 // Alarm interrupt -#define RTC_REG_2_TSF2 0X0020 // Timestamp interrupt +#define RTC_REG_2_MSF_MASK 0x0080 // Minute or second interrupt mask +#define RTC_REG_2_CDTF_MASK 0x0008 // Countdown timer interrupt mask +#define RTC_REG_2_AF_MASK 0x0010 // Alarm interrupt mask +#define RTC_REG_2_TSF2_MASK 0x0020 // Timestamp interrupt mask -#define RTC_REG_3_MASK 0X00FF -#define RTC_REG_3_BF 0x0008 +#define RTC_REG_3_BF_MASK 0x0008 // Battery status interrupt flag +#define RTC_REG_3_BLF_MASK 0x0004 // Battery status low flag -#define RTC_REG_1_INDEX 1U -#define RTC_REG_2_INDEX 2U -#define RTC_REG_3_INDEX 3U -#define RTC_SECONDS_INDEX 4U -#define RTC_MINUTES_INDEX 5U -#define RTC_HOURS_INDEX 6U -#define RTC_DAYS_INDEX 7U -#define RTC_WEEKDAYS_INDEX 8U -#define RTC_MONTHS_INDEX 9U -#define RTC_YEARS_INDEX 10U +// Indices used to check values read from RTC +#define RTC_REG_1_INDEX 1U +#define RTC_REG_2_INDEX 2U +#define RTC_REG_3_INDEX 3U +#define RTC_SECONDS_INDEX 4U +#define RTC_MINUTES_INDEX 5U +#define RTC_HOURS_INDEX 6U +#define RTC_DAYS_INDEX 7U +#define RTC_WEEKDAYS_INDEX 8U +#define RTC_MONTHS_INDEX 9U +#define RTC_YEARS_INDEX 10U -#define BUFFER_INDEX_0 0U -#define BUFFER_INDEX_1 1U -#define BUFFER_INDEX_2 2U -#define BUFFER_INDEX_3 3U -#define BUFFER_INDEX_4 4U +#define BUFFER_INDEX_0 0U +#define BUFFER_INDEX_1 1U +#define BUFFER_INDEX_2 2U +#define BUFFER_INDEX_3 3U +#define BUFFER_INDEX_4 4U -#define MIBSPI_MAX_BUFFER_LENGTH 127U -#define MIBSPI_CONTINUOUS_MODE 4U -#define MIBSPI_CHIP_SELECT_ACTIVE 1U -#define MIBSPI_CHIP_SELECT_DEACTIVE 0U -#define MIBSPI_NO_WDELAY 0U -#define MIBSPI_LOCK_TG 0U -#define MIBSPI_DATA_FORMAT_ZERO 0U -#define MIBSPI_GROUP_ZERO 0U +#define MIBSPI_MAX_BUFFER_LENGTH 127U +#define MIBSPI_CONTINUOUS_MODE 4U +#define MIBSPI_CHIP_SELECT_ACTIVE 1U +#define MIBSPI_CHIP_SELECT_DEACTIVE 0U +#define MIBSPI_NO_WDELAY 0U +#define MIBSPI_LOCK_TG 0U +#define MIBSPI_DATA_FORMAT_ZERO 0U +#define MIBSPI_GROUP_ZERO 0U -#define MIBSPI_BUFFER_MODE_BIT_SHIFT 13U -#define MIBSPI_CHIP_SELECT_BIT_SHIFT 12U -#define MIBSPI_NO_WDELAY_BIT_SHIT 10U -#define MIBSPI_LOCK_TRANS_BIT_SHIFT 11U -#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT 8U -#define MIBSPI_BUFFER_TRANS_BIT_SHIFT 8U +#define MIBSPI_BUFFER_MODE_BIT_SHIFT_13 13U +#define MIBSPI_CHIP_SELECT_BIT_SHIFT_12 12U +#define MIBSPI_NO_WDELAY_BIT_SHIT_10 10U +#define MIBSPI_LOCK_TRANS_BIT_SHIFT_11 11U +#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 8U +#define MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 8U -#define RTC_RAM_PREP_BUFFER_LENGTH 3U -#define RTC_TIMESTAMP_BUFFER_LENGTH 8U -#define RTC_GENERAL_BUFFER_LENGTH 11U +#define RTC_RAM_PREP_BUFFER_LENGTH 3U +#define RTC_TIMESTAMP_BUFFER_LENGTH 8U +#define RTC_GENERAL_BUFFER_LENGTH 11U -#define RTC_PREP_RAM_INDEX 0U -#define RTC_RAM_HIGH_ADDRESS_INDEX 1U -#define RTC_RAM_LOW_ADDRESS_INDEX 2U -#define RTC_RAM_COMMAND_INDEX 3U -#define RTC_RAM_HIGH_ADDRESS_BIT_SHIFT 8U +#define RTC_PREP_RAM_INDEX 0U +#define RTC_RAM_HIGH_ADDRESS_INDEX 1U +#define RTC_RAM_LOW_ADDRESS_INDEX 2U +#define RTC_RAM_COMMAND_INDEX 3U -#define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 -#define RTC_WRITE_TO_REG3 0x0023 // Seconds register -#define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops -#define RTC_WRITE_TO_RAM 0x003C // RTC RAM write -#define RTC_READ_FROM_RAM 0x00BD // RTC RAM read +#define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 +#define RTC_WRITE_TO_REG3 0x0023 // Seconds register +#define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops +#define RTC_WRITE_TO_RAM 0x003C // RTC RAM write +#define RTC_READ_FROM_RAM 0x00BD // RTC RAM read -#define RTC_ACCURACY_TIMEOUT 1000U // ms -#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U // ms +#define RTC_ACCURACY_TIMEOUT 1000U // ms +#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U // ms -#define TIMER_COUNTER_TO_REQUEST_READ 18U +#define TIMER_COUNTER_TO_REQUEST_READ 18U +#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U +#define MAX_ALLOWED_RTC_RAM_BYTES 100U +#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U +#define TEN 10U +#define YEAR_2000 2000U -#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U +#ifndef _VECTORCAST_ +#define EPOCH_YEAR 1970U +#else +#define EPOCH_YEAR 1900U +#define LOCAL_TO_GTM_TIME_CONVERSION 8U +#endif -#define MAX_ALLOWED_RTC_RAM_BYTES 100U -#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U - typedef enum RTC_Self_Test_States { RTC_SELF_TEST_STATE_START = 0, @@ -152,9 +159,9 @@ static RTC_TIMESTAMP_T RTCTimestampStruct; static U32 RTCSelfTestTimer = 0; -static U32 RTCPreviousSecond = 0; +static U32 RTCPreviousSecond = 0; // Previous second is used to compare seconds in POST static U32 RAMBufferLength = 0; -static U32 lastEpochTime = 0; +static U32 lastEpochTime = 0; // Last value that has been converted to epoch static U32 previousTransferLength = 0; static U32 timeCounter = 1; @@ -163,7 +170,7 @@ static BOOL hasWriteToRTCRequested = FALSE; static BOOL hasWriteToRAMRequested = FALSE; static BOOL hasReadFromRAMRequested = FALSE; -static BOOL isRTCServiceOnEntry = FALSE; +static BOOL isRTCServiceOnEntry = FALSE; static U16 rxBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; static U16 txBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; @@ -173,27 +180,27 @@ // ********** Private function prototypes ********* static BOOL serviceRTC( U16* bufferTransmit, U16* bufferReceive, U16 bufferLength ); -static BOOL isRTCFunctional(); +static BOOL isRTCFunctional( void ); static U08 convertBCD2Decimal( U08 bcd ); static U08 convertDecimal2BCD( U08 decimal ); -static U32 convertTime2Epoch(); -static void updateReadTimestampStruct(); +static U32 convertTime2Epoch( void ); +static void updateReadTimestampStruct( void ); static BOOL setMibSPIBufferLength( U16 length ); static void prepBufferForReadCommand( U08 length ); // Puts the read command -static RTC_SELF_TEST_STATE_T handleSelfTestStart(); -static RTC_SELF_TEST_STATE_T handleSelfTestCheckCtrlRegs(); -static RTC_SELF_TEST_STATE_T handleSelfTestWaitForFirstSecond(); -static RTC_SELF_TEST_STATE_T handleSelfTestWaitForSecondSecond(); -static RTC_SELF_TEST_STATE_T handleSelfTestCheckAccuracy(); +static RTC_SELF_TEST_STATE_T handleSelfTestStart( void ); +static RTC_SELF_TEST_STATE_T handleSelfTestCheckCtrlRegs( void ); +static RTC_SELF_TEST_STATE_T handleSelfTestWaitForFirstSecond( void ); +static RTC_SELF_TEST_STATE_T handleSelfTestWaitForSecondSecond( void ); +static RTC_SELF_TEST_STATE_T handleSelfTestCheckAccuracy( void ); -static RTC_EXEC_STATE_T handleExecWaitForPostState(); -static RTC_EXEC_STATE_T handleExecIdleState(); -static RTC_EXEC_STATE_T handleExecReadState(); -static RTC_EXEC_STATE_T handleExecPrepRAMState(); -static RTC_EXEC_STATE_T handleExecWriteToRAMState(); -static RTC_EXEC_STATE_T handleExecReadFromRAMState(); -static RTC_EXEC_STATE_T handleExecWriteState(); +static RTC_EXEC_STATE_T handleExecWaitForPostState( void ); +static RTC_EXEC_STATE_T handleExecIdleState( void ); +static RTC_EXEC_STATE_T handleExecReadState( void ); +static RTC_EXEC_STATE_T handleExecPrepRAMState( void ); +static RTC_EXEC_STATE_T handleExecWriteToRAMState( void ); +static RTC_EXEC_STATE_T handleExecReadFromRAMState( void ); +static RTC_EXEC_STATE_T handleExecWriteState( void ); // ********** Public functions ********** @@ -206,7 +213,7 @@ * @param none * @return none *************************************************************************/ - void initRTC() + void initRTC( void ) { RTCSelfTestState = RTC_SELF_TEST_STATE_START; RTCServiceState = RTC_SEND_COMMAND; @@ -225,22 +232,14 @@ void setRTCTimestamp( U08 secs, U08 mins, U08 hours, U08 days, U08 months, U16 years ) { hasWriteToRTCRequested = TRUE; - - U16 decimalSeconds = convertDecimal2BCD( secs ); - U16 decimalMins = convertDecimal2BCD( mins ); - U16 decimalHours = convertDecimal2BCD( hours ); - U16 decimalDays = convertDecimal2BCD( days ); - U16 decimalMonths = convertDecimal2BCD( months ); - U16 decimalYears = convertDecimal2BCD( years - 2000 ); - txBuffer[0] = RTC_WRITE_TO_REG3; txBuffer[1] = convertDecimal2BCD( secs ); txBuffer[2] = convertDecimal2BCD( mins ); txBuffer[3] = convertDecimal2BCD( hours ); txBuffer[4] = convertDecimal2BCD( days ); txBuffer[5] = 0; txBuffer[6] = convertDecimal2BCD( months ); - txBuffer[7] = convertDecimal2BCD( years - 2000 ); + txBuffer[7] = convertDecimal2BCD( years - YEAR_2000 ); } /************************************************************************* @@ -252,7 +251,7 @@ * @param none * @return SELF_TEST_STATUS_T *************************************************************************/ -SELF_TEST_STATUS_T execRTCSelfTest() +SELF_TEST_STATUS_T execRTCSelfTest( void ) { switch ( RTCSelfTestState ) { @@ -306,7 +305,7 @@ * @param none * @return none *************************************************************************/ -void execRTC() +void execRTC( void ) { switch ( RTCExecState ) { @@ -365,7 +364,7 @@ * @param none * @return lastEpochTime *************************************************************************/ -U32 getRTCTimestamp() +U32 getRTCTimestamp( void ) { return lastEpochTime; } @@ -385,6 +384,7 @@ RTC_RAM_STATUS_T writeToRAM( U16 address, U16* data, U32 length ) { RTC_RAM_STATUS_T status = RTCRAMStatus; + U08 i; if ( status == RTC_RAM_STATUS_IDLE ) { @@ -399,20 +399,14 @@ else { RTCRAMStatus = status = RTC_RAM_STATUS_IN_PROGRESS; - RTCRAMState = RTC_RAM_STATE_BUSY; - hasWriteToRAMRequested = TRUE; - RAMBufferLength = length; - txBuffer[ RTC_PREP_RAM_INDEX ] = RTC_PREP_RAM_READ_WRITE; - txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> RTC_RAM_HIGH_ADDRESS_BIT_SHIFT ); - txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & 0x00FF ); + txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> SHIFT_8_BITS_FOR_BYTE_SHIFT ); + txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & MASK_OFF_MSB ); txBuffer[ RTC_RAM_COMMAND_INDEX ] = RTC_WRITE_TO_RAM; - U08 i; - for ( i = 0; i < RAMBufferLength; i++ ) { // The first 3 elements in txBuffer are filled @@ -439,6 +433,7 @@ RTC_RAM_STATUS_T readFromRAM( U16 address, U32 length ) { RTC_RAM_STATUS_T status = RTCRAMStatus; + U08 i; if ( status == RTC_RAM_STATUS_IDLE ) { @@ -453,20 +448,14 @@ else { status = RTCRAMStatus = RTC_RAM_STATUS_IN_PROGRESS; - RTCRAMState = RTC_RAM_STATE_BUSY; - hasReadFromRAMRequested = TRUE; - RAMBufferLength = length; - txBuffer[ RTC_PREP_RAM_INDEX ] = RTC_PREP_RAM_READ_WRITE; - txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> RTC_RAM_HIGH_ADDRESS_BIT_SHIFT ); - txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & 0x00FF ); + txBuffer[ RTC_RAM_HIGH_ADDRESS_INDEX ] = ( address >> SHIFT_8_BITS_FOR_BYTE_SHIFT ); + txBuffer[ RTC_RAM_LOW_ADDRESS_INDEX ] = ( address & MASK_OFF_MSB ); txBuffer[ RTC_RAM_COMMAND_INDEX ] = RTC_READ_FROM_RAM; - U08 i; - for ( i = 0; i < length; i++ ) { txBuffer[ i + BUFFER_INDEX_4 ] = 0x0000; @@ -486,7 +475,7 @@ * @param none * @return RTC_RAM_STATE_T *************************************************************************/ -RTC_RAM_STATE_T getRTCRAMState() +RTC_RAM_STATE_T getRTCRAMState( void ) { return RTCRAMState; } @@ -501,7 +490,7 @@ * @param none * @return RTC_RAM_STATE_T *************************************************************************/ -RTC_RAM_STATUS_T getRTCRAMStatus() +RTC_RAM_STATUS_T getRTCRAMStatus( void ) { if ( RTCRAMStatus == RTC_RAM_STATUS_COMPLETE ) { @@ -563,7 +552,7 @@ static BOOL serviceRTC( U16* bufferTransmit, U16* bufferReceive, U16 bufferLength ) { BOOL result = FALSE; - BOOL bufferStatus = FALSE; + BOOL isBufferOk = FALSE; if ( isRTCServiceOnEntry ) { @@ -576,14 +565,14 @@ if ( previousTransferLength == bufferLength ) { - bufferStatus = TRUE; + isBufferOk = TRUE; } else if ( setMibSPIBufferLength( bufferLength ) ) { - bufferStatus = TRUE; + isBufferOk = TRUE; } - if ( bufferStatus ) + if ( isBufferOk ) { mibspiSetData( mibspiREG3, MIBSPI_GROUP_ZERO, bufferTransmit ); mibspiTransfer( mibspiREG3, MIBSPI_GROUP_ZERO ); @@ -644,56 +633,49 @@ * @param none * @return hasTestPassed (bool) *************************************************************************/ -static BOOL isRTCFunctional() +static BOOL isRTCFunctional( void ) { + // TODO: Add alarms BOOL hasTestPassed = TRUE; - U16 controlReg1 = rxBuffer[ RTC_REG_1_INDEX ]; U16 controlReg2 = rxBuffer[ RTC_REG_2_INDEX ]; U16 controlReg3 = rxBuffer[ RTC_REG_3_INDEX ]; + controlReg1 = controlReg1 & MASK_OFF_MSB; + controlReg2 = controlReg2 & MASK_OFF_MSB; + controlReg3 = controlReg3 & MASK_OFF_MSB; + // Ignore the clear flags - controlReg2 = controlReg2 & ~RTC_REG_2_MSF; - controlReg2 = controlReg2 & ~RTC_REG_2_CDTF; - controlReg2 = controlReg2 & ~RTC_REG_2_AF; - controlReg2 = controlReg2 & ~RTC_REG_2_TSF2; - controlReg3 = controlReg3 & ~RTC_REG_3_BF; + controlReg2 = controlReg2 & ~RTC_REG_2_MSF_MASK; + controlReg2 = controlReg2 & ~RTC_REG_2_CDTF_MASK; + controlReg2 = controlReg2 & ~RTC_REG_2_AF_MASK; + controlReg2 = controlReg2 & ~RTC_REG_2_TSF2_MASK; + controlReg3 = controlReg3 & ~RTC_REG_3_BF_MASK; - if ( controlReg1 & RTC_REG_1_12_HOUR_MODE ) + if ( controlReg1 & RTC_REG_1_12_HOUR_MODE_MASK ) { - // Set the alarm for 24 hour mode hasTestPassed = FALSE; } if ( controlReg1 & RTC_REG_1_PORO ) { - // Set the alarm for PORO low mode hasTestPassed = FALSE; } - if ( controlReg1 & RTC_REG_1_CLK_STOPPED ) + if ( controlReg1 & RTC_REG_1_CLK_STOPPED_MASK ) { - // Set the alarm for clock stopped mode hasTestPassed = FALSE; } - if ( controlReg1 & RTC_REG_1_UNUSED ) + if ( controlReg1 & RTC_REG_1_UNUSED_MASK ) { - // Set the alarm for unused bit set to 1 mode hasTestPassed = FALSE; } - if ( controlReg1 & RTC_REG_1_EXT_CLK_MODE ) + if ( controlReg1 & RTC_REG_1_EXT_CLK_MODE_MASK ) { - // Set the alarm for clock set on external mode hasTestPassed = FALSE; } - if ( controlReg2 & RTC_REG_2_MASK ) + if ( controlReg3 & RTC_REG_3_BLF_MASK ) { - // Set the alarm for register 2 hasTestPassed = FALSE; } - if ( controlReg3 & RTC_REG_3_MASK ) - { - // Set the alarm for register 3 - hasTestPassed = FALSE; - } return hasTestPassed; } @@ -713,11 +695,18 @@ U08 bcdLow; U08 decimal; - bcdHigh = ( bcd & 0xF0 ) >> 4; - bcdLow = ( bcd & 0x0F ); + bcdHigh = ( bcd & MASK_OFF_NIBBLE_LSB ) >> SHIFT_BITS_BY_4; + bcdLow = ( bcd & MASK_OFF_NIBBLE_MSB ); - decimal = ( bcdHigh * 10 ) + bcdLow; - + if ( bcdHigh > MAX_SINGLE_DIGIT_DECIMAL || bcdLow > MAX_SINGLE_DIGIT_DECIMAL ) + { + // ToDo software fault + decimal = 0; + } + else + { + decimal = ( bcdHigh * TEN ) + bcdLow; + } return decimal; } @@ -735,14 +724,17 @@ U08 decimalHigh; U08 decimalLow; U08 bcd; - - // Assuming all the decimal provided - // are maximum 2 digits - decimalHigh = decimal / 10; - decimalLow = decimal % 10; - - bcd = (decimalHigh << 4) + decimalLow; - + if ( decimal > MAX_DOUBLE_DIGIT_DECIMAL ) + { + // TODO: Add software fault + bcd = 0; + } + else + { + decimalHigh = decimal / TEN; + decimalLow = decimal % TEN; + bcd = ( decimalHigh << SHIFT_BITS_BY_4 ) + decimalLow; + } return bcd; } @@ -755,7 +747,7 @@ * @param none * @return epochTime value *************************************************************************/ -static U32 convertTime2Epoch() +static U32 convertTime2Epoch( void ) { struct tm t; time_t epochTime; @@ -764,20 +756,20 @@ t.tm_min = RTCTimestampStruct.minutes; t.tm_hour = RTCTimestampStruct.hours; t.tm_mday = RTCTimestampStruct.days; + // In epoch conversion, the months are 0-11 + // so the months is decremented t.tm_mon = RTCTimestampStruct.months - 1; + t.tm_year = RTCTimestampStruct.years + YEAR_2000 - EPOCH_YEAR; // Disabled daylight saving // If daylight saving is not disabled, MinGW in VectorCAST // may or may not calculate the value right t.tm_isdst= 0; -#ifndef _VECTORCAST_ - t.tm_year = RTCTimestampStruct.years + 2000 - 1970; -#else - t.tm_year = RTCTimestampStruct.years + 2000 - 1900; +#ifdef _VECTORCAST_ // MinGW in VectorCAST assumes the time is local while // the time is in GMT so 8 hours is subtracted from the hour // to simulate GMT for VectorCAST - t.tm_hour = t.tm_hour - 8; + t.tm_hour = t.tm_hour - LOCAL_TO_GTM_TIME_CONVERSION; #endif epochTime = mktime(&t); @@ -795,22 +787,15 @@ * @param none * @return none *************************************************************************/ -static void updateReadTimestampStruct() +static void updateReadTimestampStruct( void ) { - U16 decimalSeconds = convertBCD2Decimal( rxBuffer[ RTC_SECONDS_INDEX ] ); - U16 decimalMins = convertBCD2Decimal( rxBuffer[ RTC_MINUTES_INDEX ] ); - U16 decimalHours = convertBCD2Decimal( rxBuffer[ RTC_HOURS_INDEX ] ); - U16 decimalDays = convertBCD2Decimal( rxBuffer[ RTC_DAYS_INDEX ] ); - U16 decimalMonths = convertBCD2Decimal( rxBuffer[ RTC_MONTHS_INDEX ] ); - U16 decimalYears = convertBCD2Decimal( rxBuffer[ RTC_YEARS_INDEX ] ); - - RTCTimestampStruct.seconds = decimalSeconds; - RTCTimestampStruct.minutes = decimalMins; - RTCTimestampStruct.hours = decimalHours; - RTCTimestampStruct.days = decimalDays; + RTCTimestampStruct.seconds = convertBCD2Decimal( rxBuffer[ RTC_SECONDS_INDEX ] ); + RTCTimestampStruct.minutes = convertBCD2Decimal( rxBuffer[ RTC_MINUTES_INDEX ] ); + RTCTimestampStruct.hours = convertBCD2Decimal( rxBuffer[ RTC_HOURS_INDEX ] ); + RTCTimestampStruct.days = convertBCD2Decimal( rxBuffer[ RTC_DAYS_INDEX ] ); RTCTimestampStruct.weekdays = 0; // Weekdays will not be used - RTCTimestampStruct.months = decimalMonths; - RTCTimestampStruct.years = decimalYears; + RTCTimestampStruct.months = convertBCD2Decimal( rxBuffer[ RTC_MONTHS_INDEX ] ); + RTCTimestampStruct.years = convertBCD2Decimal( rxBuffer[ RTC_YEARS_INDEX ] ); } /************************************************************************* @@ -833,48 +818,48 @@ { U32 i = 0; - mibspiREG3->TGCTRL[0U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[0U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[1U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[1U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[1U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[1U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[2U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[2U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[2U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[2U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[3U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[3U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[3U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[3U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[4U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[4U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[4U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[4U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[5U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[5U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[5U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[5U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[6U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[6U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[6U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[6U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[7U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); - mibspiREG3->TGCTRL[7U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + mibspiREG3->TGCTRL[7U] &= ~(uint32)( (uint32)MIBSPI_MAX_BUFFER_LENGTH << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); + mibspiREG3->TGCTRL[7U] |= (uint32)( (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); - mibspiREG3->TGCTRL[8U] = (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT; + mibspiREG3->TGCTRL[8U] = (uint32)length << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8; mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) | - (uint32)( ((uint32)length - 1U) << MIBSPI_BUFFER_TRANS_BIT_SHIFT ); + (uint32)( ((uint32)length - 1U) << MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 ); while ( i < ( length - 1U ) ) { - mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ - | (uint16)( (uint16)MIBSPI_CHIP_SELECT_ACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ - | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ - | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT ) /* lock transmission */ - | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT_13 ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_ACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT_12 ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT_10 ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT_11 ) /* lock transmission */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ i++; } - mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT ) /* buffer mode */ - | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT ) /* chip select hold */ - | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT ) /* enable WDELAY */ - | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT ) /* data format */ + mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT_13 ) /* buffer mode */ + | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT_12 ) /* chip select hold */ + | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIT_10 ) /* enable WDELAY */ + | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ transferStatus = TRUE; @@ -898,9 +883,9 @@ *************************************************************************/ static void prepBufferForReadCommand( U08 length ) { + U08 i; txBuffer[ BUFFER_INDEX_0 ] = RTC_READ_FROM_REG0; - U08 i; for ( i = 1; i < length; i++ ) { txBuffer[ i ] = 0x0000; @@ -917,7 +902,7 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecWaitForPostState() +static RTC_EXEC_STATE_T handleExecWaitForPostState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_WAIT_FOR_POST; @@ -945,7 +930,7 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecIdleState() +static RTC_EXEC_STATE_T handleExecIdleState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_IDLE; @@ -984,7 +969,7 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecWriteState() +static RTC_EXEC_STATE_T handleExecWriteState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_WRITE; @@ -1018,7 +1003,7 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecPrepRAMState() +static RTC_EXEC_STATE_T handleExecPrepRAMState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_PREP_RAM; @@ -1052,26 +1037,21 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecWriteToRAMState() +static RTC_EXEC_STATE_T handleExecWriteToRAMState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_WRITE_TO_RAM; - BOOL isStatusOk = serviceRTC( txBuffer, RAMBuffer, RAMBufferLength + 1 ); if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) { result = RTC_EXEC_STATE_IDLE; - RTCRAMStatus = RTC_RAM_STATUS_COMPLETE; - hasWriteToRAMRequested = FALSE; } else if ( RTCServiceState == RTC_SERVICE_COMPLETE ) { result = RTC_EXEC_STATE_IDLE; - RTCRAMStatus = RTC_RAM_STATUS_FAILED; - hasWriteToRAMRequested = FALSE; } @@ -1087,7 +1067,7 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecReadFromRAMState() +static RTC_EXEC_STATE_T handleExecReadFromRAMState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_READ_FROM_RAM; @@ -1124,10 +1104,9 @@ * @param none * @return result (RTC_EXEC_STATE_T) *************************************************************************/ -static RTC_EXEC_STATE_T handleExecReadState() +static RTC_EXEC_STATE_T handleExecReadState( void ) { RTC_EXEC_STATE_T result = RTC_EXEC_STATE_READ; - BOOL isStatusOk = serviceRTC( txBuffer, rxBuffer, RTC_GENERAL_BUFFER_LENGTH ); if ( RTCServiceState == RTC_SERVICE_COMPLETE && isStatusOk ) @@ -1162,12 +1141,11 @@ * @param none * @return result (RTC_SELF_TEST_STATE_T) *************************************************************************/ -static RTC_SELF_TEST_STATE_T handleSelfTestStart() +static RTC_SELF_TEST_STATE_T handleSelfTestStart( void ) { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_START; - + RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; prepBufferForReadCommand( RTC_GENERAL_BUFFER_LENGTH ); - result = RTC_SELF_TEST_STATE_CHECK_CTRL_REGS; return result; @@ -1185,7 +1163,7 @@ * @param none * @return result (RTC_SELF_TEST_STATE_T) *************************************************************************/ -static RTC_SELF_TEST_STATE_T handleSelfTestCheckCtrlRegs() +static RTC_SELF_TEST_STATE_T handleSelfTestCheckCtrlRegs( void ) { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_CHECK_CTRL_REGS; @@ -1226,7 +1204,7 @@ * @param none * @return result (RTC_SELF_TEST_STATE_T) *************************************************************************/ -static RTC_SELF_TEST_STATE_T handleSelfTestWaitForFirstSecond() +static RTC_SELF_TEST_STATE_T handleSelfTestWaitForFirstSecond( void ) { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_WAIT_FOR_FIRST_SECOND; @@ -1272,7 +1250,7 @@ * @param none * @return result (RTC_SELF_TEST_STATE_T) *************************************************************************/ -static RTC_SELF_TEST_STATE_T handleSelfTestWaitForSecondSecond() +static RTC_SELF_TEST_STATE_T handleSelfTestWaitForSecondSecond( void ) { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_WAIT_FOR_SECOND_SECOND; @@ -1316,7 +1294,7 @@ * @param none * @return result (RTC_SELF_TEST_STATE_T) *************************************************************************/ -static RTC_SELF_TEST_STATE_T handleSelfTestCheckAccuracy() +static RTC_SELF_TEST_STATE_T handleSelfTestCheckAccuracy( void ) { RTC_SELF_TEST_STATE_T result = RTC_SELF_TEST_STATE_CHECK_ACCURACY; @@ -1338,7 +1316,3 @@ return result; } - - - - Index: firmware/App/Controllers/RTC.h =================================================================== diff -u -rca4b67841f4c9136401a2f1011668eb0a468f19a -r53165945d15dd7a30b3d194573507cbd31e5314f --- firmware/App/Controllers/RTC.h (.../RTC.h) (revision ca4b67841f4c9136401a2f1011668eb0a468f19a) +++ firmware/App/Controllers/RTC.h (.../RTC.h) (revision 53165945d15dd7a30b3d194573507cbd31e5314f) @@ -37,23 +37,23 @@ } RTC_RAM_STATE_T; -void initRTC(); +void initRTC( void ); -void execRTC(); +void execRTC( void ); void setRTCTimestamp( U08 secs, U08 mins, U08 hours, U08 days, U08 months, U16 years ); -U32 getRTCTimestamp(); +U32 getRTCTimestamp( void ); -SELF_TEST_STATUS_T execRTCSelfTest(); +SELF_TEST_STATUS_T execRTCSelfTest( void ); RTC_RAM_STATUS_T writeToRAM( U16 address, U16* data, U32 length ); RTC_RAM_STATUS_T readFromRAM( U16 address, U32 length ); -RTC_RAM_STATUS_T getRTCRAMStatus(); +RTC_RAM_STATUS_T getRTCRAMStatus( void ); -RTC_RAM_STATE_T getRTCRAMState(); +RTC_RAM_STATE_T getRTCRAMState( void ); void getDataFromRAM( U16* externalBuffer, U32 length ); Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u -r609937ae79b4b77a0bd9ac180d38425b0b6922fb -r53165945d15dd7a30b3d194573507cbd31e5314f --- firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 609937ae79b4b77a0bd9ac180d38425b0b6922fb) +++ firmware/App/Tasks/TaskGeneral.c (.../TaskGeneral.c) (revision 53165945d15dd7a30b3d194573507cbd31e5314f) @@ -49,47 +49,6 @@ // manage data received from other sub-systems //execSystemCommRx(); - // FOR DEBUGGING PURPOSES ONLY REMOVE - // PLEASE DO NOT REVIEW THIS CODE - // Used 120 and 200 so it will not read or write during POST - /*static U16 test = 0; - RTC_RAM_STATUS_T status = getRTCRAMStatus(); - RTC_RAM_STATE_T state = getRTCRAMState(); - static U16 returndata[5]; - static BOOL readRAM = FALSE; - static U16 data[5]; - - if ( test >=120 && test%120 == 0 ) - { - if ( state == RTC_RAM_STATE_READY ) - { - U16 test1 = test/10; - data[0] = test1; - data[1] = test1+1; - data[2] = test1+2; - data[3] = test1+3; - data[4] = test1+4; - status = writeToRAM(122, &data[0], 5); - } - } - - if ( test >= 120 && test%133 == 0 ) - { - if ( state == RTC_RAM_STATE_READY ) - { - readFromRAM(122, 5); - readRAM = TRUE; - } - } - else if ( status == RTC_RAM_STATUS_IDLE && readRAM) - { - getDataFromRAM(&returndata[0], 5); - readRAM = FALSE; - } - test++; */ - // FOR DEBUGGING PURPOSES ONLY REMOVE - // PLEASE DO NOT REVIEW THIS CODE - // Control RTC // After CommRx and and before execOperationModes() execRTC();