Index: firmware/App/Controllers/Valves.c =================================================================== diff -u -re5c6383e93940c2722d3bf73beb1d13a6d3eae6e -r9a7aa0eb2e11048600d3a189859217a82a854ebc --- firmware/App/Controllers/Valves.c (.../Valves.c) (revision e5c6383e93940c2722d3bf73beb1d13a6d3eae6e) +++ firmware/App/Controllers/Valves.c (.../Valves.c) (revision 9a7aa0eb2e11048600d3a189859217a82a854ebc) @@ -244,10 +244,10 @@ #define VBA_VALVE_CHECK ( VALVE_PID_CHECK << ( VBA_POS * VALVE_CHECK_BITS_PER_VALVE ) ) #define VBV_VALVE_CHECK ( VALVE_PID_CHECK << ( VBV_POS * VALVE_CHECK_BITS_PER_VALVE ) ) -#define VDI_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( 2 * VALVE_CHECK_BITS_PER_VALVE ) ) ) -#define VDO_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( 3 * VALVE_CHECK_BITS_PER_VALVE ) ) ) -#define VBA_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( 0 * VALVE_CHECK_BITS_PER_VALVE ) ) ) -#define VBV_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( 1 * VALVE_CHECK_BITS_PER_VALVE ) ) ) +#define VDI_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( VDI_POS * VALVE_CHECK_BITS_PER_VALVE ) ) ) +#define VDO_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( VDO_POS * VALVE_CHECK_BITS_PER_VALVE ) ) ) +#define VBA_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( VBA_POS * VALVE_CHECK_BITS_PER_VALVE ) ) ) +#define VBV_VALVE_CHECK_MASK ( ( VALVE_CHECK_MASK << ( VBV_POS * VALVE_CHECK_BITS_PER_VALVE ) ) ) static const U16 VALVE_CHECK[ NUM_OF_VALVES ][ NUM_OF_VALVE_CHECK_ENTRIES ] = { { VDI_VALVE_CHECK, VDI_VALVE_CHECK_MASK }, @@ -1061,7 +1061,6 @@ } return result; - } /*********************************************************************//** Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r1145e9197855b4f2cb79eb407d3899059b0ca410 -r9a7aa0eb2e11048600d3a189859217a82a854ebc --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 1145e9197855b4f2cb79eb407d3899059b0ca410) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 9a7aa0eb2e11048600d3a189859217a82a854ebc) @@ -297,8 +297,7 @@ // FPGA data static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data. static FPGA_SENSORS_T fpgaSensorReadings; ///< Record of last received FPGA priority sensor data. -static FPGA_ACTUATORS_T fpgaActuatorSetPoints; ///< Record of next transmitted FPGA priority actuator data. -static U08 fpgaReadByteSize; ///< FPGA read byte size. +static FPGA_ACTUATORS_T fpgaActuatorSetPoints; ///< Record of next transmitted FPGA priority actuator data.static U32 fpgaReadByteSize; ///< FPGA read byte size. // ********** private function prototypes ********** @@ -518,7 +517,6 @@ *************************************************************************/ void execFPGAIn( void ) { - fpgaReadByteSize = sizeof( FPGA_SENSORS_T ); // Check if FE or OE error has occurred checkFPGAFEOEFailure(); @@ -570,11 +568,7 @@ *************************************************************************/ void execFPGAOut( void ) { - fpgaReadByteSize = sizeof( FPGA_SENSORS_T ); - // Check if FE or OE error has occurred - checkFPGAFEOEFailure(); - // FPGA outgoing state machine switch ( fpgaState ) { @@ -790,15 +784,15 @@ // did FPGA ACK the read command? if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK ) { - U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize; + U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof( FPGA_SENSORS_T ); U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); // does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { // capture the read values - memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize ); + memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_SENSORS_T ) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } else // bad CRC @@ -881,7 +875,7 @@ U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms ); U32 const diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms ); - if ( getCurrentOperationMode() != DG_MODE_INIT ) + if ( getCurrentOperationMode() != MODE_INIT ) { if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE ) { @@ -2357,7 +2351,6 @@ } return status; - } /*********************************************************************//** @@ -2388,7 +2381,6 @@ } return status; - } /**@}*/ Index: firmware/App/Services/Interrupts.c =================================================================== diff -u -r1145e9197855b4f2cb79eb407d3899059b0ca410 -r9a7aa0eb2e11048600d3a189859217a82a854ebc --- firmware/App/Services/Interrupts.c (.../Interrupts.c) (revision 1145e9197855b4f2cb79eb407d3899059b0ca410) +++ firmware/App/Services/Interrupts.c (.../Interrupts.c) (revision 9a7aa0eb2e11048600d3a189859217a82a854ebc) @@ -44,8 +44,6 @@ #define MAX_COMM_ERRORS 5 ///< Maximum number of a given comm error for a given time window. #define COMM_ERROR_TIME_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< Time window for comm error counts. -#define MAX_FPGA_HDW_COMM_ERRORS 5 ///< Maximum number of a given FPGA HDW comm errors for a given time window. -#define FPGA_HDW_COMM_ERROR_TIME_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< Time window for FPGA HDW comm error counts. #define HET1_EDGE_BP_ROTOR_HALL_SENSOR 0 ///< HET1 edge detector associated with blood pump rotor hall sensor. #define HET1_EDGE_DPO_ROTOR_HALL_SENSOR 1 ///< HET1 edge detector associated with dialysate outlet pump rotor hall sensor. @@ -290,7 +288,7 @@ { BOOL returnValue = sci2FEOEError; - if (TRUE == sci2FEOEError ) + if ( TRUE == returnValue ) { sci2FEOEError = FALSE; }