Index: firmware/App/Controllers/RTC.c
===================================================================
diff -u -r451eb63c75e6af4d6498b598a7001eb5433a812d -rdfdd3cf20e2c41415a6b16d5b0c9dc53819b7399
--- firmware/App/Controllers/RTC.c	(.../RTC.c)	(revision 451eb63c75e6af4d6498b598a7001eb5433a812d)
+++ firmware/App/Controllers/RTC.c	(.../RTC.c)	(revision dfdd3cf20e2c41415a6b16d5b0c9dc53819b7399)
@@ -204,7 +204,7 @@
  * @param none
  * @return none
  *************************************************************************/
-void initRTC()
+ void initRTC()
 {
     RTCSelfTestState  = RTC_SELF_TEST_STATE_START;
 }
@@ -530,6 +530,18 @@
 }
 
 // ********** Private functions *********
+
+void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
+{
+
+}
+
+void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
+{
+
+}
+
+
 /*************************************************************************
  * @brief serviceRTC
  * The serviceRTC is the interface to the RTC chip:
@@ -651,27 +663,27 @@
     controlReg2 = controlReg2 & ~RTC_REG_2_TSF2;
     controlReg3 = controlReg3 & ~RTC_REG_3_BF;
 
-    if ( ! controlReg1 & RTC_REG_1_12_HOUR_MODE )
+    if ( controlReg1 & RTC_REG_1_12_HOUR_MODE )
     {
         // Set the alarm for 24 hour mode
         hasTestPassed = FALSE;
     }
-    if ( ! controlReg1 & RTC_REG_1_PORO )
+    if ( controlReg1 & RTC_REG_1_PORO )
     {
         // Set the alarm for PORO low mode
         hasTestPassed = FALSE;
     }
-    if ( ! controlReg1 & RTC_REG_1_CLK_STOPPED )
+    if ( controlReg1 & RTC_REG_1_CLK_STOPPED )
     {
         // Set the alarm for clock stopped mode
         hasTestPassed = FALSE;
     }
-    if ( ! controlReg1 & RTC_REG_1_UNUSED )
+    if ( controlReg1 & RTC_REG_1_UNUSED )
     {
         // Set the alarm for unused bit set to 1 mode
         hasTestPassed = FALSE;
     }
-    if ( ! controlReg1 & RTC_REG_1_EXT_CLK_MODE )
+    if ( controlReg1 & RTC_REG_1_EXT_CLK_MODE )
     {
         // Set the alarm for clock set on external mode
         hasTestPassed = FALSE;
@@ -847,15 +859,13 @@
                                       | (uint16)( (uint16)MIBSPI_NO_WDELAY          << MIBSPI_NO_WDELAY_BIT_SHIT )          /* enable WDELAY */
                                       | (uint16)( (uint16)MIBSPI_LOCK_TG            << MIBSPI_LOCK_TRANS_BIT_SHIFT )        /* lock transmission */
                                       | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO   << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT )  /* data format */
-                                      /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
                                       | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU );                    /* chip select */
             i++;
         }
         mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE        << MIBSPI_BUFFER_MODE_BIT_SHIFT )       /* buffer mode */
                                   | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE   << MIBSPI_CHIP_SELECT_BIT_SHIFT )       /* chip select hold */
                                   | (uint16)( (uint16)MIBSPI_NO_WDELAY              << MIBSPI_NO_WDELAY_BIT_SHIT )          /* enable WDELAY */
                                   | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO       << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT )  /* data format */
-                                      /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
                                   | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU );                        /* chip select */
 
         transferStatus = TRUE;
@@ -981,7 +991,7 @@
 
         result = RTC_EXEC_STATE_IDLE;
     }
-    else if ( RTCServiceState == RTC_SERVICE_COMPLETE && ! isStatusOk )
+    else if ( RTCServiceState == RTC_SERVICE_COMPLETE && !isStatusOk )
     {
         result = RTC_EXEC_STATE_FAULT;
 
Index: firmware/HD.dil
===================================================================
diff -u -ra635fc9674913460c74831add7886c85d8aaf8f1 -rdfdd3cf20e2c41415a6b16d5b0c9dc53819b7399
--- firmware/HD.dil	(.../HD.dil)	(revision a635fc9674913460c74831add7886c85d8aaf8f1)
+++ firmware/HD.dil	(.../HD.dil)	(revision dfdd3cf20e2c41415a6b16d5b0c9dc53819b7399)
@@ -1,4 +1,4 @@
-# RM46L852PGE 12/03/19 15:47:31
+# RM46L852PGE 12/30/19 17:07:32
 # 
 ARCH=RM46L852PGE
 # 
@@ -1846,7 +1846,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0
@@ -1865,7 +1865,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4
 DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1
@@ -1914,7 +1914,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0
@@ -2162,7 +2162,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4
 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000
-DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0
@@ -2563,7 +2563,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=102
 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16
-DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0
Index: firmware/include/mibspi.h
===================================================================
diff -u -ra635fc9674913460c74831add7886c85d8aaf8f1 -rdfdd3cf20e2c41415a6b16d5b0c9dc53819b7399
--- firmware/include/mibspi.h	(.../mibspi.h)	(revision a635fc9674913460c74831add7886c85d8aaf8f1)
+++ firmware/include/mibspi.h	(.../mibspi.h)	(revision dfdd3cf20e2c41415a6b16d5b0c9dc53819b7399)
@@ -191,7 +191,7 @@
 
 
 #define MIBSPI3_GCR1_CONFIGVALUE     (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
-#define MIBSPI3_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+#define MIBSPI3_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U))
 #define MIBSPI3_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
 #define MIBSPI3_PCFUN_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
Index: firmware/source/mibspi.c
===================================================================
diff -u -ra635fc9674913460c74831add7886c85d8aaf8f1 -rdfdd3cf20e2c41415a6b16d5b0c9dc53819b7399
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision a635fc9674913460c74831add7886c85d8aaf8f1)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision dfdd3cf20e2c41415a6b16d5b0c9dc53819b7399)
@@ -450,12 +450,12 @@
     mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
                      | (uint32)((uint32)0U << 9U)  /* TXINT */
                      | (uint32)((uint32)0U << 8U)  /* RXINT */
-                     | (uint32)((uint32)0U << 6U)  /* OVRNINT */
-                     | (uint32)((uint32)0U << 4U)  /* BITERR */
-                     | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                     | (uint32)((uint32)1U << 6U)  /* OVRNINT */
+                     | (uint32)((uint32)1U << 4U)  /* BITERR */
+                     | (uint32)((uint32)1U << 3U)  /* DESYNC */
                      | (uint32)((uint32)0U << 2U)  /* PARERR */
-                     | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
-                     | (uint32)((uint32)0U << 0U); /* DLENERR */
+                     | (uint32)((uint32)1U << 1U)  /* TIMEOUT */
+                     | (uint32)((uint32)1U << 0U); /* DLENERR */
 
     /** @b initialize @b MIBSPI3 @b Port */