Index: FPGA.c =================================================================== diff -u -r3402723ffaf9fb1256d51fd23f4273ad7c087836 -r9512aac6feeb1379d6d425361fa78d58f75c86f6 --- FPGA.c (.../FPGA.c) (revision 3402723ffaf9fb1256d51fd23f4273ad7c087836) +++ FPGA.c (.../FPGA.c) (revision 9512aac6feeb1379d6d425361fa78d58f75c86f6) @@ -48,76 +48,76 @@ /// Enumeration of FPGA states. typedef enum FPGA_States { - FPGA_STATE_START = 0, ///< Start state for the FPGA. - FPGA_STATE_READ_HEADER, ///< Read header command state for the FPGA. - FPGA_STATE_RCV_HEADER, ///< Receive header state for the FPGA. - FPGA_STATE_WRITE_ALL_ACTUATORS, ///< Write actuators command state for the FPGA. - FPGA_STATE_RCV_ALL_SENSORS, ///< Receive sensors state for the FPGA. - FPGA_STATE_FAILED, ///< Failed state for the FPGA. - NUM_OF_FPGA_STATES ///< Number of FPGA states. + FPGA_STATE_START = 0, ///< Start state for the FPGA. + FPGA_STATE_READ_HEADER, ///< Read header command state for the FPGA. + FPGA_STATE_RCV_HEADER, ///< Receive header state for the FPGA. + FPGA_STATE_WRITE_ALL_ACTUATORS, ///< Write actuators command state for the FPGA. + FPGA_STATE_RCV_ALL_SENSORS, ///< Receive sensors state for the FPGA. + FPGA_STATE_FAILED, ///< Failed state for the FPGA. + NUM_OF_FPGA_STATES ///< Number of FPGA states. } FPGA_STATE_T; -#define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. +#define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. -#define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. -#define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. -#define FPGA_BULK_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. +#define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. +#define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. +#define FPGA_BULK_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. -#define FPGA_WRITE_CMD_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA write command buffer byte length. -#define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. -#define FPGA_WRITE_RSP_BUFFER_LEN 8 ///< FPGA write command response buffer byte length. -#define FPGA_READ_RSP_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA read command response buffer byte length. +#define FPGA_WRITE_CMD_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA write command buffer byte length. +#define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. +#define FPGA_WRITE_RSP_BUFFER_LEN 8 ///< FPGA write command response buffer byte length. +#define FPGA_READ_RSP_BUFFER_LEN (FPGA_PAGE_SIZE+8) ///< FPGA read command response buffer byte length. -#define FPGA_WRITE_CMD_CODE 0x55 ///< FPGA write command code. -#define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. -#define FPGA_WRITE_CMD_ACK 0xA5 ///< FPGA write command ACK code. -#define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. -#define FPGA_CMD_NAK 0xEE ///< FPGA command NAK code. +#define FPGA_WRITE_CMD_CODE 0x55 ///< FPGA write command code. +#define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. +#define FPGA_WRITE_CMD_ACK 0xA5 ///< FPGA write command ACK code. +#define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. +#define FPGA_CMD_NAK 0xEE ///< FPGA command NAK code. -#define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. -#define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. -#define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. -#define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. -#define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. +#define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. +#define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. +#define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. +#define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. +#define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. -#define SCI2_RECEIVE_DMA_REQUEST 28 ///< Serial port 2 receive DMA request line. -#define SCI2_TRANSMIT_DMA_REQUEST 29 ///< Serial port 2 transmit DMA request line. +#define SCI2_RECEIVE_DMA_REQUEST 28 ///< Serial port 2 receive DMA request line. +#define SCI2_TRANSMIT_DMA_REQUEST 29 ///< Serial port 2 transmit DMA request line. -#define FPGA_INPUT_VOLTAGE_SCALE 3.0F ///< FPGA source and aux voltage. -#define FPGA_PVN_VOLTAGE_SCALE 1.0F ///< FPGA pvn voltage. +#define FPGA_INPUT_VOLTAGE_SCALE 3.0F ///< FPGA source and aux voltage. +#define FPGA_PVN_VOLTAGE_SCALE 1.0F ///< FPGA pvn voltage. -#define FPGA_ADC1_AUTO_READ_ENABLE 0x01 ///< Auto-read enable bit for ADC1 control register. +#define FPGA_ADC1_AUTO_READ_ENABLE 0x01 ///< Auto-read enable bit for ADC1 control register. -#define FPGA_AIRTRAP_LEVEL_LOW_MASK 0x0008 ///< Bit mask for air trap lower level sensor. -#define FPGA_AIRTRAP_LEVEL_HIGH_MASK 0x0004 ///< Bit mask for air trap upper level sensor. +#define FPGA_AIRTRAP_LEVEL_LOW_MASK 0x0008 ///< Bit mask for air trap lower level sensor. +#define FPGA_AIRTRAP_LEVEL_HIGH_MASK 0x0004 ///< Bit mask for air trap upper level sensor. -#define FPGA_FLUID_LEAK_STATE_MASK 0x0040 ///< Bit mask for fluid leak detector. +#define FPGA_FLUID_LEAK_STATE_MASK 0x0040 ///< Bit mask for fluid leak detector. -#define FPGA_BLOOD_LEAK_STATUS_MASK 0x1000 ///< Bit mask for blood leak detector. -#define FPGA_BLOOD_LEAK_ST_BIT_INDEX 12 ///< Bit index for the blood leak self test status bit. -#define FPGA_BLOOD_LEAK_ZERO_STATE_MASK 0x2000 ///< Bit mask for blood leak detector zero. -#define FPAG_BLOOD_LEAK_ZERO_BIT_INDEX 13 ///< Bit index for the blood leak zero status bit. -#define FPGA_BLOOD_LEAK_ZERO_CMD 0x02 ///< Bit for blood leak detector zero command. -#define FPGA_BLOOD_LEAK_SELF_TEST_CMD 0x01 ///< Bit for blood leak detector self test command. +#define FPGA_BLOOD_LEAK_STATUS_MASK 0x1000 ///< Bit mask for blood leak detector. +#define FPGA_BLOOD_LEAK_ST_BIT_INDEX 12 ///< Bit index for the blood leak self test status bit. +#define FPGA_BLOOD_LEAK_ZERO_STATE_MASK 0x2000 ///< Bit mask for blood leak detector zero. +#define FPAG_BLOOD_LEAK_ZERO_BIT_INDEX 13 ///< Bit index for the blood leak zero status bit. +#define FPGA_BLOOD_LEAK_ZERO_CMD 0x02 ///< Bit for blood leak detector zero command. +#define FPGA_BLOOD_LEAK_SELF_TEST_CMD 0x01 ///< Bit for blood leak detector self test command. -#define FPGA_ADA_BUBBLE_STATUS_MASK 0x0001 ///< Bit mask for arterial air bubble detector input status. -#define FPGA_ADV_BUBBLE_STATUS_MASK 0x0002 ///< Bit mask for venous air bubble detector input status. -#define FPGA_ADA_BUBBLE_SELF_TEST_CMD 0x04 ///< Bit for arterial air bubble detector self-test command. -#define FPGA_ADV_BUBBLE_SELF_TEST_CMD 0x08 ///< Bit for venous air bubble detector self-test command. +#define FPGA_ADA_BUBBLE_STATUS_MASK 0x0001 ///< Bit mask for arterial air bubble detector input status. +#define FPGA_ADV_BUBBLE_STATUS_MASK 0x0002 ///< Bit mask for venous air bubble detector input status. +#define FPGA_ADA_BUBBLE_SELF_TEST_CMD 0x04 ///< Bit for arterial air bubble detector self-test command. +#define FPGA_ADV_BUBBLE_SELF_TEST_CMD 0x08 ///< Bit for venous air bubble detector self-test command. -#define FPGA_PBO_TEMP_DIVISOR 2047.0F ///< Used in conversion of PBo temperature reading to deg C. -#define FPGA_PBO_TEMP_GAIN 200.0F ///< Used in conversion of PBo temperature reading to deg C. -#define FPGA_PBO_TEMP_OFFSET 50.0F ///< Used in conversion of PBo temperature reading to deg C. +#define FPGA_PBO_TEMP_DIVISOR 2047.0F ///< Used in conversion of PBo temperature reading to deg C. +#define FPGA_PBO_TEMP_GAIN 200.0F ///< Used in conversion of PBo temperature reading to deg C. +#define FPGA_PBO_TEMP_OFFSET 50.0F ///< Used in conversion of PBo temperature reading to deg C. -#define FPGA_ALARM_AUDIO_VOLUME_SHIFT 3 ///< Shift alarm audio volume 3 bits to left before writing to register. -#define FPGA_ALARM_AUDIO_DIVIDE_SHIFT 6 ///< Shift alarm audio volume divider 6 bits to left before writing to register. +#define FPGA_ALARM_AUDIO_VOLUME_SHIFT 3 ///< Shift alarm audio volume 3 bits to left before writing to register. +#define FPGA_ALARM_AUDIO_DIVIDE_SHIFT 6 ///< Shift alarm audio volume divider 6 bits to left before writing to register. -#define FPGA_BACKUP_ALARM_AUDIO_CONVERT 0.4F ///< Converts backup (piezo) alarm audio ADC volts to amps. +#define FPGA_BACKUP_ALARM_AUDIO_CONVERT 0.4F ///< Converts backup (piezo) alarm audio ADC volts to amps. -#define FRONT_DOOR_SWITCH_MASK 0x0010 ///< Front door switch bit mask. Bit 4 of the GPIO register. -#define PUMP_TRACK_SWITCH_MASK 0x0020 ///< Pump track switch bit mask. Bit 5 of the GPIO register. +#define FRONT_DOOR_SWITCH_MASK 0x0010 ///< Front door switch bit mask. Bit 4 of the GPIO register. +#define PUMP_TRACK_SWITCH_MASK 0x0020 ///< Pump track switch bit mask. Bit 5 of the GPIO register. -#define FPGA_VALVES_MIN_PWM_MODE_COUNT 2500 ///< FPGA valves minimum PWM in PWM mode in counts. +#define FPGA_VALVES_MIN_PWM_MODE_COUNT 2500 ///< FPGA valves minimum PWM in PWM mode in counts. // ********** private data ********** @@ -174,9 +174,9 @@ /*********************************************************************//** * @brief - * The initFPGA function initializes the FPGA module. - * @details Inputs: none - * @details Outputs: FPGA module initialized. + * The initFPGA function initializes the FPGA unit. + * @details \b Inputs: none + * @details \b Outputs: FPGA unit initialized. * @return none *************************************************************************/ void initFPGA( U08* hdr, U08* sen, U08* act, U32 hdrSize, U32 senSize, U32 actSize ) @@ -288,8 +288,8 @@ * @brief * The resetFPGACommFlags function resets the various fpga comm flags and * counters. - * @details Inputs: none - * @details Outputs: fpga comm flags & counters reset + * @details \b Inputs: none + * @details \b Outputs: fpga comm flags and counters reset * @return none *************************************************************************/ static void resetFPGACommFlags( void ) @@ -306,9 +306,12 @@ /*********************************************************************//** * @brief * The signalFPGAReceiptCompleted function increments a counter to indicate - * that another DMA receipt from the FPGA has completed. - * @details Inputs: none - * @details Outputs: fpgaReceiptCounter + * that another DMA receipt from the FPGA has completed and sets comm flags + * indicating pending response from FPGA is completed. + * @details \b Inputs: none + * @details \b Outputs: fpgaReceiptCounter, fpgaWriteCommandInProgress, + * fpgaWriteCommandResponseReceived, fpgaReadCommandInProgress, + * fpgaReadCommandResponseReceived, fpgaBulkWriteAndReadInProgress * @return none *************************************************************************/ void signalFPGAReceiptCompleted( void ) @@ -341,8 +344,8 @@ * @brief * The signalFPGATransmitCompleted function increments a counter to indicate * that another DMA transmit to the FPGA has completed. - * @details Inputs: none - * @details Outputs: fpgaReceiptCounter + * @details \b Inputs: none + * @details \b Outputs: fpgaTransmitCounter * @return none *************************************************************************/ void signalFPGATransmitCompleted( void ) @@ -353,16 +356,20 @@ /*********************************************************************//** * @brief * The execFPGA function manages incoming data exchanges with the FPGA. - * @details Inputs: fpgaState - * @details Outputs: fpgaState + * @details \b Alarm: ALARM_ID_XX_SOFTWARE_FAULT if current FPGA state is invalid. + * @details \b Inputs: fpgaState + * @details \b Outputs: fpgaState + * @param in Flag indicating whether we are executing the in or out cycle of the state machine. * @return none *************************************************************************/ -void execFPGAIn( void ) +void execFPGA( BOOL in ) { + if ( TRUE == in ) + { + // Check if FE or OE error has occurred + checkFPGAFEOEFailure(); + } - // Check if FE or OE error has occurred - checkFPGAFEOEFailure(); - // FPGA incoming state machine switch ( fpgaState ) { @@ -378,42 +385,6 @@ fpgaState = handleFPGAReceiveAllSensorsState(); break; - case FPGA_STATE_FAILED: - // Do nothing - we will be stuck here - break; - - default: - if ( fpgaState >= NUM_OF_FPGA_STATES ) - { - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_IN_STATE, fpgaState ) - } - else - { - // Ok, some states handled in the outgoing state machine - } - break; - } - - // Reset comm flags after processing incoming responses - resetFPGACommFlags(); - - // Monitor the power status - monitorFPGAPowerStatus(); -} - -/*********************************************************************//** - * @brief - * The execFPGAOut function manages outgoing data exchanges with the FPGA. - * @details Inputs: fpgaState - * @details Outputs: fpgaState - * @return none - *************************************************************************/ -void execFPGAOut( void ) -{ - - // FPGA outgoing state machine - switch ( fpgaState ) - { case FPGA_STATE_READ_HEADER: fpgaState = handleFPGAReadHeaderState(); break; @@ -427,24 +398,34 @@ break; default: - if ( fpgaState >= NUM_OF_FPGA_STATES ) - { - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_OUT_STATE, fpgaState ) - } - else - { - // Ok, some states handled in the incoming state machine - } +#ifdef _TD_ + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_STATE, fpgaState ) +#endif +#ifdef _DD_ + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_STATE, fpgaState ) +#endif +#ifdef _RO_ + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_RO_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_STATE, fpgaState ) +#endif break; } + + if ( TRUE == in ) + { + // Reset comm flags after processing incoming responses + resetFPGACommFlags(); + + // Monitor the power status + monitorFPGAPowerStatus(); + } } /*********************************************************************//** * @brief * The handleFPGAReadHeaderState function handles the FPGA state where - * the read header registers command is sent to the FPGA. - * @details Inputs: none - * @details Outputs: read command sent to FPGA + * the read FPGA header registers command is sent to the FPGA. + * @details \b Inputs: none + * @details \b Outputs: read header command transmit to FPGA is initiated * @return next FPGA state *************************************************************************/ static FPGA_STATE_T handleFPGAReadHeaderState( void ) @@ -474,8 +455,8 @@ * @brief * The handleFPGAReceiveHeaderState function handles the FPGA state * where the header registers read response should be ready to take in. - * @details Inputs: none - * @details Outputs: header register values updated + * @details \b Inputs: fpgaReadCommandResponseReceived, fpgaReadResponseBuffer[] + * @details \b Outputs: header register values updated * @return next FPGA state *************************************************************************/ static FPGA_STATE_T handleFPGAReceiveHeaderState( void ) @@ -523,9 +504,10 @@ /*********************************************************************//** * @brief * The handleFPGAWriteAllActuatorsState function handles the FPGA state - * where the bulk write command is sent to the FPGA. - * @details Inputs: actuator set points - * @details Outputs: actuator set points sent to FPGA + * where the bulk write and read commands are setup for DMA and the builk + * write command transmit to FPGA is initiated. + * @details \b Inputs: actuator set points + * @details \b Outputs: fpgaWriteCmdBuffer[], fpgaReadCmdBuffer[] * @return next FPGA state *************************************************************************/ static FPGA_STATE_T handleFPGAWriteAllActuatorsState( void ) @@ -573,9 +555,12 @@ /*********************************************************************//** * @brief * The handleFPGAReceiveAllSensorsState function handles the FPGA state - * where the bulk read response should be ready to parse. - * @details Inputs: none - * @details Outputs: sensor values updated + * where the bulk write and read responses should be ready to parse. The + * bulk write command response is checked to ensure FPGA acknowledged it. + * The bulk read command response is CRC checked and registers updated. + * @details \b Inputs: fpgaWriteCommandResponseReceived, fpgaWriteResponseBuffer[], + * fpgaReadCommandResponseReceived, fpgaReadResponseBuffer[] + * @details \b Outputs: Register (sensor) values updated * @return next FPGA state *************************************************************************/ static FPGA_STATE_T handleFPGAReceiveAllSensorsState( void ) @@ -662,10 +647,10 @@ /*********************************************************************//** * @brief * The consumeUnexpectedData function checks to see if a byte is sitting in - * the SCI2 received data register. - * @details Inputs: fpgaHeader - * @details Outputs: none - * @return fpgaDiag + * the SCI2 received data register and consumes the byte if found. + * @details \b Inputs: SCI FLR register + * @details \b Outputs: SCI errors cleared, unexpected byte consumed + * @return none *************************************************************************/ static void consumeUnexpectedData( void ) { @@ -682,8 +667,8 @@ /*********************************************************************//** * @brief * The monitorFPGAPowerStatus function monitors the status of the FPGA power source. - * @details Inputs: none - * @details Outputs: none + * @details \b Inputs: TBD + * @details \b Outputs: TBD * @return none *************************************************************************/ static void monitorFPGAPowerStatus( void ) @@ -695,8 +680,8 @@ * @brief * The setupDMAForWriteCmd function sets the byte count for the next DMA * write command to the FPGA. - * @details Inputs: none - * @details Outputs: number of bytes for next FPGA write command is set + * @details \b Inputs: none + * @details \b Outputs: number of bytes for next FPGA write command is set * @param bytes2Transmit number of bytes to be transmitted via DMA to the FPGA * @return none *************************************************************************/ @@ -717,8 +702,8 @@ * @brief * The startDMAWriteCmd function initiates the DMA transmit for the next * DMA write command to the FPGA. - * @details Inputs: none - * @details Outputs: DMA write command to FPGA is initiated + * @details \b Inputs: fpgaDMAWriteControlRecord + * @details \b Outputs: DMA write command to FPGA is initiated * @return none *************************************************************************/ static void startDMAWriteCmd( void ) @@ -732,8 +717,9 @@ * @brief * The setupDMAForWriteResp function sets the expected byte count for the * next DMA write command response from the FPGA. - * @details Inputs: none - * @details Outputs: number of expected bytes for next FPGA write command response is set + * @details \b Alarm: ALARM_ID_XX_SOFTWARE_FAULT if byte count exceeds buffer size. + * @details \b Inputs: none + * @details \b Outputs: fpgaDMAWriteRespControlRecord * @param bytes2Receive number of bytes expected to be transmitted via DMA from the FPGA * @return none *************************************************************************/ @@ -754,8 +740,8 @@ * @brief * The startDMAReceiptOfWriteResp function initiates readiness of the DMA * receiver for the next DMA write command response from the FPGA. - * @details Inputs: none - * @details Outputs: DMA write command response is ready to be received from the FPGA + * @details \b Inputs: fpgaDMAWriteRespControlRecord + * @details \b Outputs: DMA write command response is made ready to be received from the FPGA * @return none *************************************************************************/ static void startDMAReceiptOfWriteResp( void ) @@ -769,8 +755,9 @@ * @brief * The setupDMAForReadCmd function sets the byte count for the next DMA * read command to the FPGA. - * @details Inputs: none - * @details Outputs: number of bytes for next FPGA read command is set + * @details \b Alarm: ALARM_ID_XX_SOFTWARE_FAULT if byte count exceeds buffer size. + * @details \b Inputs: none + * @details \b Outputs: fpgaDMAReadControlRecord * @param bytes2Transmit number of bytes to be transmitted via DMA to the FPGA * @return none *************************************************************************/ @@ -791,8 +778,8 @@ * @brief * The startDMAReadCmd function initiates the DMA transmit for the next * DMA read command to the FPGA. - * @details Inputs: none - * @details Outputs: DMA read command to FPGA is initiated + * @details \b Inputs: fpgaDMAReadControlRecord + * @details \b Outputs: DMA read command to FPGA is initiated * @return none *************************************************************************/ static void startDMAReadCmd( void ) @@ -806,8 +793,9 @@ * @brief * The setupDMAForReadResp function sets the expected byte count for the * next DMA read command response from the FPGA. - * @details Inputs: none - * @details Outputs: number of expected bytes for next FPGA read command response is set + * @details \b Alarm: ALARM_ID_XX_SOFTWARE_FAULT if byte count exceeds buffer size. + * @details \b Inputs: none + * @details \b Outputs: fpgaDMAReadRespControlRecord * @param bytes2Receive number of expected bytes to be transmitted via DMA from the FPGA * @return none *************************************************************************/ @@ -828,8 +816,8 @@ * @brief * The startDMAReceiptOfReadResp function initiates readiness of the DMA * receiver for the next DMA read command response from the FPGA. - * @details Inputs: none - * @details Outputs: DMA read command response is ready to be received from the FPGA + * @details \b Inputs: fpgaDMAReadRespControlRecord + * @details \b Outputs: DMA read command response is ready to be received from the FPGA * @return none *************************************************************************/ static void startDMAReceiptOfReadResp( void )