Index: FPGA.c
===================================================================
diff -u -rf77e7c2b1dab61807f21f25c793afc063d43907c -r3ca022103ce50b39e5d805b7577c7f360730412d
--- FPGA.c	(.../FPGA.c)	(revision f77e7c2b1dab61807f21f25c793afc063d43907c)
+++ FPGA.c	(.../FPGA.c)	(revision 3ca022103ce50b39e5d805b7577c7f360730412d)
@@ -1,17 +1,17 @@
 /**************************************************************************
 *
-* Copyright (c) 2019-2024 Diality Inc. - All Rights Reserved.
+* Copyright (c) 2024-2024 Diality Inc. - All Rights Reserved.
 *
 * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
 * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
 *
 * @file    FPGA.c
 *
 * @author  (last)      Sean Nash
-* @date    (last)      10-Sep-2023
+* @date    (last)      31-Jul-2024
 *
-* @author  (original)  Dara Navaei
-* @date    (original)  05-Nov-2019
+* @author  (original)  Sean Nash
+* @date    (original)  31-Jul-2024
 *
 ***************************************************************************/
 
@@ -60,8 +60,8 @@
 #define FPGA_PAGE_SIZE                  256                             ///< FPGA register pages are 256 bytes.
 
 #define FPGA_HEADER_START_ADDR          0x0000                          ///< Start address for FPGA header data.
+#define FPGA_BULK_WRITE_START_ADDR      0x0004                          ///< Start address for FPGA continuous priority writes.
 #define FPGA_BULK_READ_START_ADDR       0x0100                          ///< Start address for FPGA continuous priority reads.
-#define FPGA_BULK_WRITE_START_ADDR      0x000B                          ///< Start address for FPGA continuous priority writes.
 
 #define FPGA_WRITE_CMD_BUFFER_LEN       (FPGA_PAGE_SIZE+8)              ///< FPGA write command buffer byte length.
 #define FPGA_READ_CMD_BUFFER_LEN        8                               ///< FPGA read command buffer byte length.
@@ -150,6 +150,12 @@
  * The initFPGA function initializes the FPGA unit.
  * @details \b Inputs: none
  * @details \b Outputs: FPGA unit initialized.
+ * @param hdr Pointer to the FPGA header register I/O map record.
+ * @param sen Pointer to the FPGA sensor register I/O map record.
+ * @param act Pointer to the FPGA actuator register I/O map record.
+ * @param hdrSize Size (in bytes) of the FPGA header register I/O map record.
+ * @param senSize Size (in bytes) of the FPGA sensor register I/O map record.
+ * @param actSize Size (in bytes) of the FPGA actuator register I/O map record.
  * @return none
  *************************************************************************/
 void initFPGA( U08* hdr, U08* sen, U08* act, U32 hdrSize, U32 senSize, U32 actSize )
@@ -188,8 +194,8 @@
     fpgaDMAWriteControlRecord.CHCTRL = 0;                        // No chaining
     fpgaDMAWriteControlRecord.ELCNT = 1;                         // Frame is 1 element
     fpgaDMAWriteControlRecord.FRCNT = 0;                         // Block is TBD frames - will be populated later when known
-    fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT;             // Element size is 1 byte
-    fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT;             //
+    fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT;             // Element size is 1 byte for read
+    fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT;             // Element size is 1 byte for write
     fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER;            // Transfer type is block transfer
     fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1;             // Source addressing mode is post-increment
     fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED;            // Dest. addressing mode is fixed
@@ -477,7 +483,7 @@
 /*********************************************************************//**
  * @brief
  * The handleFPGAWriteAllActuatorsState function handles the FPGA state
- * where the bulk write and read commands are setup for DMA and the builk
+ * where the bulk write and read commands are setup for DMA and the bulk
  * write command transmit to FPGA is initiated.
  * @details \b Inputs: actuator set points
  * @details \b Outputs: fpgaWriteCmdBuffer[], fpgaReadCmdBuffer[]
@@ -667,7 +673,15 @@
     }
     else
     {
+#ifdef _TD_
         SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit )
+#endif
+#ifdef _DD_
+       SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit );
+#endif
+#ifdef _RO_
+       SET_ALARM_WITH_2_U32_DATA( ALARM_ID_RO_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit );
+#endif
     }
 }
 
@@ -705,7 +719,15 @@
     }
     else
     {
+#ifdef _TD_
         SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
+#ifdef _DD_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
+#ifdef _RO_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_RO_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
     }
 }
 
@@ -743,7 +765,15 @@
     }
     else
     {
+#ifdef _TD_
         SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit )
+#endif
+#ifdef _DD_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit )
+#endif
+#ifdef _RO_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_RO_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit )
+#endif
     }
 }
 
@@ -781,7 +811,15 @@
     }
     else
     {
+#ifdef _TD_
         SET_ALARM_WITH_2_U32_DATA( ALARM_ID_TD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
+#ifdef _DD_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DD_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
+#ifdef _RO_
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_RO_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive )
+#endif
     }
 }