Index: firmware/App/Services/SystemCommTD.c =================================================================== diff -u -r3518e8a088c32e75c0c8960d5e629a7401095feb -r380b0afc95467d0861ff3aa2cdcde5d5d7ac85e7 --- firmware/App/Services/SystemCommTD.c (.../SystemCommTD.c) (revision 3518e8a088c32e75c0c8960d5e629a7401095feb) +++ firmware/App/Services/SystemCommTD.c (.../SystemCommTD.c) (revision 380b0afc95467d0861ff3aa2cdcde5d5d7ac85e7) @@ -36,15 +36,15 @@ // ********** private definitions ********** -#define UI_COMM_TIMEOUT_IN_MS 7500 ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD. -#define UI_COMM_SERVICE_MODE_TIMEOUT_IN_MS (2 * SEC_PER_MIN * MS_PER_SECOND) ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD when in service mode. -#define DG_COMM_TIMEOUT_IN_MS 1000 ///< DG has not checked in for this much time +#define UI_COMM_TIMEOUT_IN_MS 7500 ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD. +#define UI_COMM_SERVICE_MODE_TIMEOUT_IN_MS (2 * SEC_PER_MIN * MS_PER_SECOND) ///< Maximum time (in ms) that UI is allowed to wait before checking in with HD when in service mode. +#define DG_COMM_TIMEOUT_IN_MS 1000 ///< DG has not checked in for this much time -#define MAX_COMM_CRC_FAILURES 5 ///< Maximum number of CRC errors within window period before alarm -#define MAX_COMM_CRC_FAILURE_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< CRC error window +#define MAX_COMM_CRC_FAILURES 5 ///< Maximum number of CRC errors within window period before alarm +#define MAX_COMM_CRC_FAILURE_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< CRC error window -#define MAX_FPGA_CLOCK_SPEED_ERRORS 3 ///< maximum number of FPGA clock speed errors within window period before alarm -#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< FPGA clock speed error window +#define MAX_FPGA_CLOCK_SPEED_ERRORS 3 ///< maximum number of FPGA clock speed errors within window period before alarm +#define MAX_FPGA_CLOCK_SPEED_ERROR_WINDOW_MS (10 * SEC_PER_MIN * MS_PER_SECOND) ///< FPGA clock speed error window /// Array of out-going CAN buffers. const COMM_BUFFER_T CAN_OUT_BUFFERS[ NUM_OF_CAN_OUT_BUFFERS ] =