/************************************************************************** * * Copyright (c) 2020-2023 Diality Inc. - All Rights Reserved. * * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. * * @file DGCommon.h * * @author (last) Dara Navaei * @date (last) 12-Oct-2022 * * @author (original) Sean * @date (original) 27-Feb-2020 * ***************************************************************************/ #ifndef __DG_COMMON_H__ #define __DG_COMMON_H__ #include "hal_stdtypes.h" // ********** version ********** #define DG_VERSION_MAJOR 0 #define DG_VERSION_MINOR 6 #define DG_VERSION_MICRO 0 #define DG_VERSION_BUILD 177 // ********** build switches ********** #ifndef _RELEASE_ #ifndef _VECTORCAST_ // #define BOARD_WITH_NO_HARDWARE 1 // Build switch // #define TASK_TIMING_OUTPUT_ENABLED 1 // Build switch // re-purposes drain pump enable pin for task timing #include #include #endif #endif #include "Common.h" /** * @defgroup CommonDGHeader CommonDGHeader * @brief Provides commonly used definitions and macros for DG firmware. * * @addtogroup CommonDGHeader * @{ */ // **** Common Definitions **** #pragma pack(push,1) /// DG version struct. typedef struct { U08 major; ///< DG version major revision U08 minor; ///< DG version major revision U08 micro; ///< DG version micro revision U16 build; ///< DG build version U08 fpgaId; ///< DG FPGA ID U08 fpgaMajor; ///< DG FPGA major revision U08 fpgaMinor; ///< DG FPGA minor revision U08 fpgaLab; ///< DG FPGA lab revision U32 compatibilityRev; ///< DG compatibility revision } DG_VERSIONS_T; #pragma pack(pop) // **** Common Macros **** /**@}*/ // **** VectorCAST Definitions **** #ifdef _VECTORCAST_ #endif #endif