-- VectorCAST 19.sp3 (11/13/19) -- Test Case Script -- -- Environment : FPGA -- Unit(s) Under Test: FPGA -- -- Script Features TEST.SCRIPT_FEATURE:C_DIRECT_ARRAY_INDEXING TEST.SCRIPT_FEATURE:CPP_CLASS_OBJECT_REVISION TEST.SCRIPT_FEATURE:MULTIPLE_UUT_SUPPORT TEST.SCRIPT_FEATURE:MIXED_CASE_NAMES TEST.SCRIPT_FEATURE:STATIC_HEADER_FUNCS_IN_UUTS TEST.SCRIPT_FEATURE:VCAST_MAIN_NOT_RENAMED -- -- Unit: FPGA -- Subprogram: consumeUnexpectedData -- Test Case: DataBytePending TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:DataBytePending TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:1 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady uut_prototype_stubs.sciReceiveByte FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Test Case: NoData TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:NoData TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:0 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Subprogram: execFPGAIn -- Test Case: CommErrorTooManyRetries TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:CommErrorTooManyRetries TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaCommRetryCount:5 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:6 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:InvalidState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 114 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_SOFTWARE_FAULT >>> >>> Value for 'Enumeral' out of range >>> >>> Read "ALARM_ID_SOFTWARE_FAULT" >>> >>> Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_SOFTWARE_FAULT TEST.END -- Test Case: OutgoingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:OutgoingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: RcvAllSensorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvAllSensorsState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:0x7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:0x8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0x9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[11]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[12]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[13]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[14]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[15]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[16]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[19]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[20]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[21]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[22]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[23]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[24]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[25]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[26]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[27]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[28]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[29]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[30]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[31]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[32]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[33]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[34]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[35]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[36]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[37]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[38]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[39]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[40]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[41]:0x0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:0 TEST.EXPECTED:uut_prototype_stubs.crc16.len:163 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: RcvHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvHeaderState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 261 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0x0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 275 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x403 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:0x12 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:0x34 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:1 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:2 TEST.EXPECTED:uut_prototype_stubs.crc16.len:17 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.END -- Test Case: StartState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:StartState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Subprogram: execFPGAOut -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.END -- Test Case: IncomingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:IncomingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:InvalidState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 336 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_SOFTWARE_FAULT >>> >>> Value for 'Enumeral' out of range >>> >>> Read "ALARM_ID_SOFTWARE_FAULT" >>> >>> Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_SOFTWARE_FAULT TEST.END -- Test Case: ReadHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:ReadHeaderState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:14 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:19 TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.END -- Test Case: WriteAllActuatorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:WriteAllActuatorsState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[0]:0x55 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[1]:2 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:1 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:160 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.EXPECTED:uut_prototype_stubs.crc16.len:27,4 TEST.END -- Subprogram: execFPGATest -- Test Case: TestFailed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestFailed TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x58 TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_FAILED TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarm:ALARM_ID_FPGA_POST_TEST_FAILED TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarmData.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarmData.data.uInt.data:0x58 TEST.END -- Test Case: TestPassed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestPassed TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x5A TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_PASSED TEST.END -- Subprogram: getFPGAAccelAxes -- Test Case: getFPGAAccelAxes_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelAxes TEST.NEW TEST.NAME:getFPGAAccelAxes_NominalPath TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 467 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:00 >>> >>> Warning: Value already set >>> >>> Previous value 12 ignored >>> (E) @LINE: 468 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 >>> >>> Warning: Value already set >>> >>> Previous value 23 ignored >>> (E) @LINE: 469 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 >>> >>> Warning: Value already set >>> >>> Previous value 56 ignored >>> (E) @LINE: 478 TEST.EXPECTED:FPGA.getFPGAAccelAxes.x[0]:0 >>> >>> Warning: Value already set >>> >>> Previous value 12 ignored >>> (E) @LINE: 479 TEST.EXPECTED:FPGA.getFPGAAccelAxes.y[0]:0 >>> >>> Warning: Value already set >>> >>> Previous value 23 ignored >>> (E) @LINE: 480 TEST.EXPECTED:FPGA.getFPGAAccelAxes.z[0]:256 >>> >>> Warning: Value already set >>> >>> Previous value 56 ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelAxes.x:<> TEST.VALUE:FPGA.getFPGAAccelAxes.x[0]:1 TEST.VALUE:FPGA.getFPGAAccelAxes.y:<> TEST.VALUE:FPGA.getFPGAAccelAxes.y[0]:2 TEST.VALUE:FPGA.getFPGAAccelAxes.z:<> TEST.VALUE:FPGA.getFPGAAccelAxes.z[0]:3 TEST.EXPECTED:FPGA.getFPGAAccelAxes.x[0]:0 TEST.EXPECTED:FPGA.getFPGAAccelAxes.y[0]:0 TEST.EXPECTED:FPGA.getFPGAAccelAxes.z[0]:256 TEST.END -- Subprogram: getFPGAAccelMaxes -- Test Case: getFPGAAccelMaxes_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelMaxes TEST.NEW TEST.NAME:getFPGAAccelMaxes_NominalPath TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 505 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 >>> >>> Warning: Value already set >>> >>> Previous value 15 ignored >>> (E) @LINE: 506 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 >>> >>> Warning: Value already set >>> >>> Previous value 16 ignored >>> (E) @LINE: 507 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 >>> >>> Warning: Value already set >>> >>> Previous value 17 ignored >>> (E) @LINE: 513 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.xmax[0]:10 >>> >>> Warning: Value already set >>> >>> Previous value 15 ignored >>> (E) @LINE: 514 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.zmax[0]:20 >>> >>> Warning: Value already set >>> >>> Previous value 17 ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelMaxes.xmax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.xmax[0]:1 TEST.VALUE:FPGA.getFPGAAccelMaxes.ymax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.ymax[0]:2 TEST.VALUE:FPGA.getFPGAAccelMaxes.zmax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.zmax[0]:3 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.xmax[0]:10 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.ymax[0]:-11 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.zmax[0]:20 TEST.END -- Subprogram: getFPGAAccelStatus -- Test Case: getFPGAAccelStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelStatus TEST.NEW TEST.NAME:getFPGAAccelStatus_NominalPath TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 538 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 >>> >>> Warning: Value already set >>> >>> Previous value 18 ignored >>> (E) @LINE: 539 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 >>> >>> Warning: Value already set >>> >>> Previous value 17 ignored >>> (E) @LINE: 542 TEST.EXPECTED:FPGA.getFPGAAccelStatus.cnt[0]:11 >>> >>> Warning: Value already set >>> >>> Previous value 17 ignored >>> (E) @LINE: 543 TEST.EXPECTED:FPGA.getFPGAAccelStatus.err[0]:0 >>> >>> Warning: Value already set >>> >>> Previous value 18 ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelStatus.cnt:<> TEST.VALUE:FPGA.getFPGAAccelStatus.cnt[0]:1 TEST.VALUE:FPGA.getFPGAAccelStatus.err:<> TEST.VALUE:FPGA.getFPGAAccelStatus.err[0]:22 TEST.EXPECTED:FPGA.getFPGAAccelStatus.cnt[0]:11 TEST.EXPECTED:FPGA.getFPGAAccelStatus.err[0]:0 TEST.END -- Subprogram: getFPGAAirTrapLevels -- Test Case: getFPGAAirTrapLevels_AirLow_FluidHigh TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAirTrapLevels TEST.NEW TEST.NAME:getFPGAAirTrapLevels_AirLow_FluidHigh TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x8 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower[0]:2 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:2 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtLower[0]:1 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:0 TEST.END -- Test Case: getFPGAAirTrapLevels_FluidLow_AirHigh TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAirTrapLevels TEST.NEW TEST.NAME:getFPGAAirTrapLevels_FluidLow_AirHigh TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x4 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower[0]:2 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:2 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtLower[0]:0 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:1 TEST.END -- Subprogram: getFPGAArterialPressure -- Test Case: getFPGAArterialPressure_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAArterialPressure TEST.NEW TEST.NAME:getFPGAArterialPressure_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1Channel0:0x807FFF9C TEST.EXPECTED:FPGA.getFPGAArterialPressure.return:-100 TEST.END -- Subprogram: getFPGABloodFlow -- Test Case: getFPGABloodFlow_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodFlow TEST.NEW TEST.NAME:getFPGABloodFlow_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowLast:403.2 TEST.EXPECTED:FPGA.getFPGABloodFlow.return:403.2 TEST.END -- Subprogram: getFPGABloodFlowSignalStrength -- Test Case: getFPGABloodFlowSignalStrength_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodFlowSignalStrength TEST.NEW TEST.NAME:getFPGABloodFlowSignalStrength_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowSignalStrength:0.90 TEST.EXPECTED:FPGA.getFPGABloodFlowSignalStrength.return:0.90 TEST.END -- Subprogram: getFPGABloodPumpHallSensorCount -- Test Case: getFPGABloodPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpHallSensorCount TEST.NEW TEST.NAME:getFPGABloodPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodPumpHallSensorCount:1234 TEST.EXPECTED:FPGA.getFPGABloodPumpHallSensorCount.return:1234 TEST.END -- Subprogram: getFPGABloodPumpHallSensorStatus -- Test Case: getFPGABloodPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGABloodPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodPumpHallSensorStatus:0x47 TEST.EXPECTED:FPGA.getFPGABloodPumpHallSensorStatus.return:0x47 TEST.END -- Subprogram: getFPGABloodPumpOcclusion -- Test Case: getFPGABloodPumpOcclusion_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpOcclusion TEST.NEW TEST.NAME:getFPGABloodPumpOcclusion_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodOcclusionData:400 TEST.EXPECTED:FPGA.getFPGABloodPumpOcclusion.return:400 TEST.END -- Subprogram: getFPGADialInPumpHallSensorCount -- Test Case: getFPGADialInPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialInPumpHallSensorCount TEST.NEW TEST.NAME:getFPGADialInPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialInPumpHallSensorCount:2345 TEST.EXPECTED:FPGA.getFPGADialInPumpHallSensorCount.return:2345 TEST.END -- Subprogram: getFPGADialInPumpHallSensorStatus -- Test Case: getFPGADialInPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialInPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGADialInPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialInPumpHallSensorStatus:0x83 TEST.EXPECTED:FPGA.getFPGADialInPumpHallSensorStatus.return:0x83 TEST.END -- Subprogram: getFPGADialInPumpOcclusion -- Test Case: getFPGADialInPumpOcclusion_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialInPumpOcclusion TEST.NEW TEST.NAME:getFPGADialInPumpOcclusion_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateInOcclusionData:400 TEST.EXPECTED:FPGA.getFPGADialInPumpOcclusion.return:400 TEST.END -- Subprogram: getFPGADialOutPumpHallSensorCount -- Test Case: getFPGADialOutPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialOutPumpHallSensorCount TEST.NEW TEST.NAME:getFPGADialOutPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialOutPumpHallSensorCount:0xD374 TEST.EXPECTED:FPGA.getFPGADialOutPumpHallSensorCount.return:0xD374 TEST.END -- Subprogram: getFPGADialOutPumpHallSensorStatus -- Test Case: getFPGADialOutPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialOutPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGADialOutPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialOutPumpSensorStatus:0xFA TEST.EXPECTED:FPGA.getFPGADialOutPumpHallSensorStatus.return:0xFA TEST.END -- Subprogram: getFPGADialOutPumpOcclusion -- Test Case: getFPGADialOutPumpOcclusion_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialOutPumpOcclusion TEST.NEW TEST.NAME:getFPGADialOutPumpOcclusion_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateOutOcclusionData:400 TEST.EXPECTED:FPGA.getFPGADialOutPumpOcclusion.return:400 TEST.END -- Subprogram: getFPGADialysateFlow -- Test Case: getFPGADialysateFlow_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialysateFlow TEST.NEW TEST.NAME:getFPGADialysateFlow_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowLast:299.3 TEST.EXPECTED:FPGA.getFPGADialysateFlow.return:299.3 TEST.END -- Subprogram: getFPGADialysateFlowSignalStrength -- Test Case: getFPGADialysateFlowSignalStrength_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialysateFlowSignalStrength TEST.NEW TEST.NAME:getFPGADialysateFlowSignalStrength_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowSignalStrength:0.9 TEST.EXPECTED:FPGA.getFPGADialysateFlowSignalStrength.return:0.90 TEST.END -- Subprogram: getFPGAValveBloodArterialCurrentCounts -- Test Case: getFPGAValveBloodArterialCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodArterialCurrentCounts TEST.NEW TEST.NAME:getFPGAValveBloodArterialCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBACurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodArterialCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodArterialCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodArterialPosition -- Test Case: getFPGAValveBloodArterialPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodArterialPosition TEST.NEW TEST.NAME:getFPGAValveBloodArterialPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBAPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodArterialPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodArterialPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodVenousCurrentCounts -- Test Case: getFPGAValveBloodVenousCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodVenousCurrentCounts TEST.NEW TEST.NAME:getFPGAValveBloodVenousCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBVCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodVenousCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodVenousCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodVenousPosition -- Test Case: getFPGAValveBloodVenousPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodVenousPosition TEST.NEW TEST.NAME:getFPGAValveBloodVenousPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBVPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodVenousPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodVenousPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerInletCurrentCounts -- Test Case: getFPGAValveDialyzerInletCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerInletCurrentCounts TEST.NEW TEST.NAME:getFPGAValveDialyzerInletCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDiCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerInletCurrentCounts.return:0x800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerInletCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerInletPosition -- Test Case: getFPGAValveDialyzerInletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerInletPosition TEST.NEW TEST.NAME:getFPGAValveDialyzerInletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDiPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerInletPosition.return:01440 TEST.EXPECTED:FPGA.getFPGAValveDialyzerInletPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerOutletCurrentCounts -- Test Case: getFPGAValveDialyzerOutletCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerOutletCurrentCounts TEST.NEW TEST.NAME:getFPGAValveDialyzerOutletCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDoCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerOutletCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerOutletCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerOutletPosition -- Test Case: getFPGAValveDialyzerOutletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerOutletPosition TEST.NEW TEST.NAME:getFPGAValveDialyzerOutletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDoPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerOutletPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerOutletPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValvesStatus -- Test Case: getFPGAValvesStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValvesStatus TEST.NEW TEST.NAME:getFPGAValvesStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.valveStatus:0x1234 TEST.VALUE:FPGA.getFPGAValvesStatus.return:34 TEST.EXPECTED:FPGA.getFPGAValvesStatus.return:0x1234 TEST.END -- Subprogram: getFPGAVenousPressure -- Test Case: getFPGAVenousPressure_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVenousPressure TEST.NEW TEST.NAME:getFPGAVenousPressure_NominalPath TEST.EXPECTED:FPGA.getFPGAVenousPressure.return:0 TEST.END -- Subprogram: getFPGAVersions -- Test Case: getFPGAVersions_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVersions TEST.NEW TEST.NAME:getFPGAVersions_NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x5A TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:2 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRevMajor:1 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRevLab:3 TEST.VALUE:FPGA.getFPGAVersions.Id:<> TEST.VALUE:FPGA.getFPGAVersions.Maj:<> TEST.VALUE:FPGA.getFPGAVersions.Min:<> TEST.VALUE:FPGA.getFPGAVersions.Lab:<> TEST.EXPECTED:FPGA.getFPGAVersions.Id[0]:0x5A TEST.EXPECTED:FPGA.getFPGAVersions.Maj[0]:1 TEST.EXPECTED:FPGA.getFPGAVersions.Min[0]:2 TEST.EXPECTED:FPGA.getFPGAVersions.Lab[0]:3 TEST.END -- Subprogram: handleFPGAReadHeaderState -- Test Case: NominalCase TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReadHeaderState TEST.NEW TEST.NAME:NominalCase TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:14 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:19 TEST.EXPECTED:FPGA.handleFPGAReadHeaderState.return:FPGA_STATE_RCV_HEADER TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[3]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[4]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]::INPUT_BASE=16 TEST.END -- Subprogram: handleFPGAReceiveAllSensorsState -- Test Case: BadCRC TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:BadCRC TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[127]:0x11 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[128]:0x34 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:uut_prototype_stubs.crc16.len:163 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[42]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[87]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<