-- VectorCAST 19.sp3 (11/13/19)
-- Test Case Script
-- 
-- Environment    : COMM
-- Unit(s) Under Test: Comm
-- 
-- Script Features
TEST.SCRIPT_FEATURE:C_DIRECT_ARRAY_INDEXING
TEST.SCRIPT_FEATURE:CPP_CLASS_OBJECT_REVISION
TEST.SCRIPT_FEATURE:MULTIPLE_UUT_SUPPORT
TEST.SCRIPT_FEATURE:MIXED_CASE_NAMES
TEST.SCRIPT_FEATURE:STATIC_HEADER_FUNCS_IN_UUTS
TEST.SCRIPT_FEATURE:VCAST_MAIN_NOT_RENAMED
--

-- Unit: Comm

-- Subprogram: clearSCI1CommErrors

-- Test Case: clearSCI1CommErrors_NominalPath
TEST.UNIT:Comm
TEST.SUBPROGRAM:clearSCI1CommErrors
TEST.NEW
TEST.NAME:clearSCI1CommErrors_NominalPath
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci1REG[0].FLR:0
TEST.EXPECTED:Comm.<<GLOBAL>>.ptr_sci1REG[0].FLR:0x6000000
TEST.ATTRIBUTES:Comm.<<GLOBAL>>.ptr_sci2REG[0].FLR:INPUT_BASE=16,EXPECTED_BASE=16
TEST.END

-- Subprogram: clearSCI2DMAReceiveInterrupt

-- Test Case: clearSCI2DMAReceiveInterrupt
TEST.UNIT:Comm
TEST.SUBPROGRAM:clearSCI2DMAReceiveInterrupt
TEST.NEW
TEST.NAME:clearSCI2DMAReceiveInterrupt
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].CLEARINT:0
TEST.EXPECTED:Comm.<<GLOBAL>>.ptr_sci2REG[0].CLEARINT:0x60000
TEST.END

-- Subprogram: clearSCI2DMATransmitInterrupt

-- Test Case: clearSCI2DMATransmitInterrupt
TEST.UNIT:Comm
TEST.SUBPROGRAM:clearSCI2DMATransmitInterrupt
TEST.NEW
TEST.NAME:clearSCI2DMATransmitInterrupt
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].CLEARINT:0
TEST.EXPECTED:Comm.<<GLOBAL>>.ptr_sci2REG[0].CLEARINT:0x10000
TEST.END

-- Subprogram: isCAN1TransmitInProgress

-- Test Case: isCAN1TransmitInProgress_Ch1_8_Busy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isCAN1TransmitInProgress
TEST.NEW
TEST.NAME:isCAN1TransmitInProgress_Ch1_8_Busy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[0]:1
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[1]:0
TEST.EXPECTED:Comm.isCAN1TransmitInProgress.return:1
TEST.END

-- Test Case: isCAN1TransmitInProgress_Ch9_16_Busy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isCAN1TransmitInProgress
TEST.NEW
TEST.NAME:isCAN1TransmitInProgress_Ch9_16_Busy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[0]:0
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[1]:1
TEST.EXPECTED:Comm.isCAN1TransmitInProgress.return:1
TEST.END

-- Test Case: isCAN1TransmitInProgress_InProgress
TEST.UNIT:Comm
TEST.SUBPROGRAM:isCAN1TransmitInProgress
TEST.NEW
TEST.NAME:isCAN1TransmitInProgress_InProgress
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[0..1]:0
TEST.VALUE:Comm.<<GLOBAL>>.canXmitsInProgress:1
TEST.EXPECTED:Comm.isCAN1TransmitInProgress.return:1
TEST.END

-- Test Case: isCAN1TransmitInProgress_NotBusy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isCAN1TransmitInProgress
TEST.NEW
TEST.NAME:isCAN1TransmitInProgress_NotBusy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_can1REG[0].TXRQx[0..1]:0
TEST.EXPECTED:Comm.isCAN1TransmitInProgress.return:0
TEST.END

-- Subprogram: isSCI2DMATransmitInProgress

-- Test Case: isSCI2DMATransmitInProgress_DMABusy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isSCI2DMATransmitInProgress
TEST.NEW
TEST.NAME:isSCI2DMATransmitInProgress_DMABusy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG[0].PEND:0x4
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].FLR:0x100
TEST.EXPECTED:Comm.isSCI2DMATransmitInProgress.return:1
TEST.END

-- Test Case: isSCI2DMATransmitInProgress_NotBusy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isSCI2DMATransmitInProgress
TEST.NEW
TEST.NAME:isSCI2DMATransmitInProgress_NotBusy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG[0].PEND:0
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].FLR:0x100
TEST.EXPECTED:Comm.isSCI2DMATransmitInProgress.return:0
TEST.END

-- Test Case: isSCI2DMATransmitInProgress_TransmitterBusy
TEST.UNIT:Comm
TEST.SUBPROGRAM:isSCI2DMATransmitInProgress
TEST.NEW
TEST.NAME:isSCI2DMATransmitInProgress_TransmitterBusy
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_dma1REG[0].PEND:0
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].FLR:0
TEST.EXPECTED:Comm.isSCI2DMATransmitInProgress.return:1
TEST.END

-- Subprogram: setSCI2DMAReceiveInterrupt

-- Test Case: setSCI2DMAReceiveInterrupt
TEST.UNIT:Comm
TEST.SUBPROGRAM:setSCI2DMAReceiveInterrupt
TEST.NEW
TEST.NAME:setSCI2DMAReceiveInterrupt
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].SETINT:0
TEST.EXPECTED:Comm.<<GLOBAL>>.ptr_sci2REG[0].SETINT:0x60000
TEST.END

-- Subprogram: setSCI2DMATransmitInterrupt

-- Test Case: setSCI2DMATransmitInterrupt
TEST.UNIT:Comm
TEST.SUBPROGRAM:setSCI2DMATransmitInterrupt
TEST.NEW
TEST.NAME:setSCI2DMATransmitInterrupt
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG:<<malloc 1>>
TEST.VALUE:Comm.<<GLOBAL>>.ptr_sci2REG[0].SETINT:0
TEST.EXPECTED:Comm.<<GLOBAL>>.ptr_sci2REG[0].SETINT:0x10000
TEST.ATTRIBUTES:Comm.<<GLOBAL>>.ptr_sci1REG[0].SETINT:EXPECTED_BASE=16
TEST.END

-- Subprogram: signalCANXmitsCompleted

-- Test Case: signalCANXmitsCompleted_NominalPath
TEST.UNIT:Comm
TEST.SUBPROGRAM:signalCANXmitsCompleted
TEST.NEW
TEST.NAME:signalCANXmitsCompleted_NominalPath
TEST.VALUE:Comm.<<GLOBAL>>.canXmitsInProgress:1
TEST.EXPECTED:Comm.<<GLOBAL>>.canXmitsInProgress:0
TEST.END

-- Subprogram: signalCANXmitsInitiated

-- Test Case: signalCANXmitsInitiated_NominalPath
TEST.UNIT:Comm
TEST.SUBPROGRAM:signalCANXmitsInitiated
TEST.NEW
TEST.NAME:signalCANXmitsInitiated_NominalPath
TEST.VALUE:Comm.<<GLOBAL>>.canXmitsInProgress:0
TEST.EXPECTED:Comm.<<GLOBAL>>.canXmitsInProgress:1
TEST.END