-- VectorCAST 19.sp3 (11/13/19) -- Test Case Script -- -- Environment : FPGA -- Unit(s) Under Test: FPGA -- -- Script Features TEST.SCRIPT_FEATURE:C_DIRECT_ARRAY_INDEXING TEST.SCRIPT_FEATURE:CPP_CLASS_OBJECT_REVISION TEST.SCRIPT_FEATURE:MULTIPLE_UUT_SUPPORT TEST.SCRIPT_FEATURE:MIXED_CASE_NAMES TEST.SCRIPT_FEATURE:STATIC_HEADER_FUNCS_IN_UUTS TEST.SCRIPT_FEATURE:VCAST_MAIN_NOT_RENAMED -- -- Unit: FPGA -- Subprogram: checkFPGACommFailure -- Test Case: checkFPGACommFailure.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGACommFailure TEST.NEW TEST.NAME:checkFPGACommFailure.001 TEST.BASIS_PATH:1 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (getMSTimerCount() > 1 * 1000) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.checkFPGACommFailure.return:1 TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.checkFPGACommFailure.return:0 TEST.END -- Test Case: checkFPGACommFailure.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGACommFailure TEST.NEW TEST.NAME:checkFPGACommFailure.002 TEST.BASIS_PATH:2 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 2 (1) if (getMSTimerCount() > 1 * 1000) ==> TRUE (2) if ((1) == incTimeWindowedCount(TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES)) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.checkFPGACommFailure.return:3 TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.return:<> TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.checkFPGACommFailure.return:0 TEST.EXPECTED:uut_prototype_stubs.incTimeWindowedCount.cnt:TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES TEST.END -- Test Case: checkFPGACommFailure.003 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGACommFailure TEST.NEW TEST.NAME:checkFPGACommFailure.003 TEST.BASIS_PATH:3 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 3 (1) if (getMSTimerCount() > 1 * 1000) ==> TRUE (2) if ((1) == incTimeWindowedCount(TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES)) ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountProcessor:10 TEST.VALUE:FPGA.checkFPGACommFailure.return:0 TEST.VALUE:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_FPGA_COMM_TIMEOUT TEST.VALUE:uut_prototype_stubs.activateAlarm2Data.alarmData1.dataType:ALARM_DATA_TYPE_U32 TEST.VALUE:uut_prototype_stubs.activateAlarm2Data.alarmData2.dataType:ALARM_DATA_TYPE_U32 TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.return:1 TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.errorCountProcessor:10 TEST.EXPECTED:FPGA.checkFPGACommFailure.return:1 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_FPGA_COMM_TIMEOUT TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData1.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData1.data.uInt.data:3 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData2.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData2.data.uInt.data:10 TEST.EXPECTED:uut_prototype_stubs.incTimeWindowedCount.cnt:TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES TEST.END -- Subprogram: checkFPGAFEOEFailure -- Test Case: checkFPGAFEOEFailure.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGAFEOEFailure TEST.NEW TEST.NAME:checkFPGAFEOEFailure.001 TEST.BASIS_PATH:1 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if ((1) == FPGAFEOEError) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.checkFPGAFEOEFailure.return:1 TEST.VALUE:uut_prototype_stubs.getSci2FEOEError.return:<> TEST.EXPECTED:FPGA.checkFPGAFEOEFailure.return:0 TEST.END -- Test Case: checkFPGAFEOEFailure.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGAFEOEFailure TEST.NEW TEST.NAME:checkFPGAFEOEFailure.002 TEST.BASIS_PATH:2 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 2 (1) if ((1) == FPGAFEOEError) ==> TRUE (2) if (getMSTimerCount() > 1 * 1000) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.checkFPGAFEOEFailure.return:1 TEST.VALUE:uut_prototype_stubs.getSci2FEOEError.return:1 TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.checkFPGAFEOEFailure.return:0 TEST.END -- Test Case: checkFPGAFEOEFailure.003 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGAFEOEFailure TEST.NEW TEST.NAME:checkFPGAFEOEFailure.003 TEST.BASIS_PATH:3 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 3 (1) if ((1) == FPGAFEOEError) ==> TRUE (2) if (getMSTimerCount() > 1 * 1000) ==> TRUE (3) if ((1) == incTimeWindowedCount(TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES)) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.checkFPGAFEOEFailure.return:1 TEST.VALUE:uut_prototype_stubs.getSci2FEOEError.return:1 TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.return:<> TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.checkFPGAFEOEFailure.return:0 TEST.END -- Test Case: checkFPGAFEOEFailure.004 TEST.UNIT:FPGA TEST.SUBPROGRAM:checkFPGAFEOEFailure TEST.NEW TEST.NAME:checkFPGAFEOEFailure.004 TEST.BASIS_PATH:4 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 4 (1) if ((1) == FPGAFEOEError) ==> TRUE (2) if (getMSTimerCount() > 1 * 1000) ==> TRUE (3) if ((1) == incTimeWindowedCount(TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES)) ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountProcessor:5 TEST.VALUE:FPGA.checkFPGAFEOEFailure.return:0 TEST.VALUE:uut_prototype_stubs.activateAlarm2Data.alarmData1.dataType:ALARM_DATA_TYPE_U32 TEST.VALUE:uut_prototype_stubs.activateAlarm2Data.alarmData2.dataType:ALARM_DATA_TYPE_U32 TEST.VALUE:uut_prototype_stubs.getSci2FEOEError.return:1 TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.return:1 TEST.VALUE:uut_prototype_stubs.getMSTimerCount.return:<> TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.errorCountProcessor:5 TEST.EXPECTED:FPGA.checkFPGAFEOEFailure.return:1 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData1.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData1.data.uInt.data:3 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData2.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarmData2.data.uInt.data:5 TEST.END -- Subprogram: clearFPGABubbleSelfTest -- Test Case: clearFPGABubbleSelfTest.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:clearFPGABubbleSelfTest TEST.NEW TEST.NAME:clearFPGABubbleSelfTest.001 TEST.MCDC_BASIS_PATH:2 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 2 (1) if (bubble == (ADA)) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #1, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.clearFPGABubbleSelfTest.bubble:0 TEST.EXPECTED:FPGA.clearFPGABubbleSelfTest.bubble:0 TEST.END -- Test Case: clearFPGABubbleSelfTest.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:clearFPGABubbleSelfTest TEST.NEW TEST.NAME:clearFPGABubbleSelfTest.002 TEST.MCDC_BASIS_PATH:1 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (bubble == (ADA)) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #1, subcondition "a". Condition a ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.clearFPGABubbleSelfTest.bubble:1 TEST.EXPECTED:FPGA.clearFPGABubbleSelfTest.bubble:1 TEST.END -- Subprogram: consumeUnexpectedData -- Test Case: DataBytePending TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:DataBytePending TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:1 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady uut_prototype_stubs.sciReceiveByte FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Test Case: NoData TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:NoData TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:0 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Subprogram: execFPGAClockSpeedTest -- Test Case: execFPGAClockSpeedTest.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAClockSpeedTest TEST.NEW TEST.NAME:execFPGAClockSpeedTest.001 TEST.VALUE:uut_prototype_stubs.getCurrentOperationMode.return:MODE_STAN TEST.VALUE:uut_prototype_stubs.u16DiffWithWrap.return:2 TEST.EXPECTED:FPGA.<>.currentFPGATimerCount_ms:0 TEST.END -- Test Case: execFPGAClockSpeedTest.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAClockSpeedTest TEST.NEW TEST.NAME:execFPGAClockSpeedTest.002 TEST.MCDC_BASIS_PATH:1 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (getCurrentOperationMode() > (MODE_INIT)) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #1, subcondition "a". Condition a ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.STUB:FPGA.getFPGATimerCount TEST.VALUE:uut_prototype_stubs.getCurrentOperationMode.return:<> TEST.EXPECTED:FPGA.<>.currentFPGATimerCount_ms:0 TEST.END -- Test Case: execFPGAClockSpeedTest.003 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAClockSpeedTest TEST.NEW TEST.NAME:execFPGAClockSpeedTest.003 TEST.MCDC_BASIS_PATH:4 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 4 (1) if (getCurrentOperationMode() > (MODE_INIT)) ==> TRUE (2) if (abs(diffFPGATimerCount - diffTimerCount) > 1) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #2, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: Cannot set return value of function abs in branch 2 TEST.END_NOTES: TEST.STUB:FPGA.getFPGATimerCount TEST.VALUE:uut_prototype_stubs.getCurrentOperationMode.return:<> TEST.EXPECTED:FPGA.<>.currentFPGATimerCount_ms:0 TEST.END -- Test Case: execFPGAClockSpeedTest.004 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAClockSpeedTest TEST.NEW TEST.NAME:execFPGAClockSpeedTest.004 TEST.VALUE:uut_prototype_stubs.getCurrentOperationMode.return:MODE_STAN TEST.VALUE:uut_prototype_stubs.u16DiffWithWrap.return:2 TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.cnt:TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR TEST.VALUE:uut_prototype_stubs.incTimeWindowedCount.return:1 TEST.EXPECTED:FPGA.<>.currentFPGATimerCount_ms:0 TEST.EXPECTED:uut_prototype_stubs.incTimeWindowedCount.cnt:TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR TEST.END -- Test Case: execFPGAClockSpeedTest.005 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAClockSpeedTest TEST.NEW TEST.NAME:execFPGAClockSpeedTest.005 TEST.BASIS_PATH:1 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (getCurrentOperationMode() != (MODE_INIT)) ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.STUB:FPGA.getFPGATimerCount TEST.VALUE:uut_prototype_stubs.getCurrentOperationMode.return:MODE_INIT TEST.EXPECTED:FPGA.<>.currentFPGATimerCount_ms:0 TEST.EXPECTED:FPGA.<>.currentTimerCount_ms:0 TEST.END -- Subprogram: execFPGAIn -- Test Case: CommErrorTooManyRetries TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:CommErrorTooManyRetries TEST.IMPORT_FAILURES: (E) @LINE: 178 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:5 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 181 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:6 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:InvalidState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 114 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_SOFTWARE_FAULT >>> >>> Value for 'Enumeral' out of range >>> >>> Read "ALARM_ID_SOFTWARE_FAULT" >>> >>> Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_SOFTWARE_FAULT TEST.END -- Test Case: OutgoingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:OutgoingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: RcvAllSensorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvAllSensorsState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 316 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterDeviceStatus >>> (E) @LINE: 327 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterDeviceStatus TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:0x7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:0x8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0x9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[11]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[12]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[13]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[14]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[15]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[16]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[19]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[20]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[21]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[22]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[23]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[24]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[25]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[26]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[27]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[28]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[29]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[30]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[31]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[32]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[33]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[34]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[35]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[36]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[37]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[38]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[39]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[40]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[41]:0x0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: RcvHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvHeaderState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 261 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0x0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 275 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x403 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:0x12 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:0x34 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: StartState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:StartState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: execFPGAIn.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:execFPGAIn.001 TEST.IMPORT_FAILURES: (E) @LINE: 433 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:6 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountProcessor:<> TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.errorCountProcessor:<> TEST.END -- Test Case: execFPGAIn.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:execFPGAIn.002 TEST.IMPORT_FAILURES: (E) @LINE: 459 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:4 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountProcessor:<> TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.errorCountProcessor:<> TEST.END -- Subprogram: execFPGAOut -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.END -- Test Case: IncomingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:IncomingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:InvalidState TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 336 TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_SOFTWARE_FAULT >>> >>> Value for 'Enumeral' out of range >>> >>> Read "ALARM_ID_SOFTWARE_FAULT" >>> >>> Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:uut_prototype_stubs.activateAlarm2Data.alarm:ALARM_ID_HD_SOFTWARE_FAULT TEST.END -- Test Case: ReadHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:ReadHeaderState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[3]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[4]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: WriteAllActuatorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:WriteAllActuatorsState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[0]:0x55 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[1]:2 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:1 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[3]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[4]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Subprogram: execFPGATest -- Test Case: TestFailed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestFailed TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 434 TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarm:ALARM_ID_FPGA_POST_TEST_FAILED >>> >>> Value for 'Enumeral' out of range >>> >>> Read "ALARM_ID_FPGA_POST_TEST_FAILED" >>> >>> Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x58 TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_FAILED TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarmData.dataType:ALARM_DATA_TYPE_U32 TEST.EXPECTED:uut_prototype_stubs.activateAlarm1Data.alarmData.data.uInt.data:0x58 TEST.END -- Test Case: TestPassed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestPassed TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x5A TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_FAILED TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[0]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[4]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[5]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[6]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[7]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[3]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[4]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: execFPGATest.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:execFPGATest.001 TEST.BASIS_PATH:3 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 3 (1) if (0x5a == fpgaHeader.fpgaId) ==> TRUE (2) if (1 == fpgaSensorReadings.fpgaCompatibilityRev) ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:90 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaCompatibilityRev:1 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:90 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.fpgaCompatibilityRev:1 TEST.END -- Subprogram: getFPGAAccelAxes -- Test Case: getFPGAAccelAxes_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelAxes TEST.NEW TEST.NAME:getFPGAAccelAxes_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelAxes.x:<> TEST.VALUE:FPGA.getFPGAAccelAxes.x[0]:1 TEST.VALUE:FPGA.getFPGAAccelAxes.y:<> TEST.VALUE:FPGA.getFPGAAccelAxes.y[0]:2 TEST.VALUE:FPGA.getFPGAAccelAxes.z:<> TEST.VALUE:FPGA.getFPGAAccelAxes.z[0]:3 TEST.EXPECTED:FPGA.getFPGAAccelAxes.x[0]:0 TEST.EXPECTED:FPGA.getFPGAAccelAxes.y[0]:0 TEST.EXPECTED:FPGA.getFPGAAccelAxes.z[0]:256 TEST.END -- Subprogram: getFPGAAccelMaxes -- Test Case: getFPGAAccelMaxes_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelMaxes TEST.NEW TEST.NAME:getFPGAAccelMaxes_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelMaxes.xmax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.xmax[0]:1 TEST.VALUE:FPGA.getFPGAAccelMaxes.ymax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.ymax[0]:2 TEST.VALUE:FPGA.getFPGAAccelMaxes.zmax:<> TEST.VALUE:FPGA.getFPGAAccelMaxes.zmax[0]:3 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.xmax[0]:10 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.ymax[0]:-11 TEST.EXPECTED:FPGA.getFPGAAccelMaxes.zmax[0]:20 TEST.END -- Subprogram: getFPGAAccelStatus -- Test Case: getFPGAAccelStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAccelStatus TEST.NEW TEST.NAME:getFPGAAccelStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelX:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelY:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZ:256 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelXMax:10 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelYMax:0xFFF5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelZMax:20 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelFaultRegister:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.accelSampleCounter:11 TEST.VALUE:FPGA.getFPGAAccelStatus.cnt:<> TEST.VALUE:FPGA.getFPGAAccelStatus.cnt[0]:1 TEST.VALUE:FPGA.getFPGAAccelStatus.err:<> TEST.VALUE:FPGA.getFPGAAccelStatus.err[0]:22 TEST.EXPECTED:FPGA.getFPGAAccelStatus.cnt[0]:11 TEST.EXPECTED:FPGA.getFPGAAccelStatus.err[0]:0 TEST.END -- Subprogram: getFPGAAirTrapLevels -- Test Case: getFPGAAirTrapLevels.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAirTrapLevels TEST.NEW TEST.NAME:getFPGAAirTrapLevels.001 TEST.MCDC_BASIS_PATH:4 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 4 (2) (0 == upper) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #2, subcondition "a". Condition a ==> FALSE Test Case Generation Notes: Cannot set local variable upper in branch 2 TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:1 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower[0]:0 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper:<> TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.fpgaGPIO:1 TEST.END -- Test Case: getFPGAAirTrapLevels_AirLow_FluidHigh TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAirTrapLevels TEST.NEW TEST.NAME:getFPGAAirTrapLevels_AirLow_FluidHigh TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x8 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower[0]:2 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:2 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtLower[0]:1 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:0 TEST.END -- Test Case: getFPGAAirTrapLevels_FluidLow_AirHigh TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAAirTrapLevels TEST.NEW TEST.NAME:getFPGAAirTrapLevels_FluidLow_AirHigh TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x4 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtLower[0]:2 TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper:<> TEST.VALUE:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:2 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtLower[0]:0 TEST.EXPECTED:FPGA.getFPGAAirTrapLevels.airAtUpper[0]:1 TEST.END -- Subprogram: getFPGAArterialPressure -- Test Case: getFPGAArterialPressure_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAArterialPressure TEST.NEW TEST.NAME:getFPGAArterialPressure_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1Channel0:0x807FFF9C TEST.EXPECTED:FPGA.getFPGAArterialPressure.return:0x807FFF9C TEST.END -- Subprogram: getFPGAArterialPressureErrorCounter -- Test Case: getFPGAArterialPressureErrorCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAArterialPressureErrorCounter TEST.NEW TEST.NAME:getFPGAArterialPressureErrorCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1ErrorCount:24 TEST.EXPECTED:FPGA.getFPGAArterialPressureErrorCounter.return:24 TEST.END -- Subprogram: getFPGAArterialPressureReadCounter -- Test Case: getFPGAArterialPressureReadCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAArterialPressureReadCounter TEST.NEW TEST.NAME:getFPGAArterialPressureReadCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1SequenceCount:34 TEST.EXPECTED:FPGA.getFPGAArterialPressureReadCounter.return:34 TEST.END -- Subprogram: getFPGABackupAlarmAudioCurrent -- Test Case: getFPGABackupAlarmAudioCurrent.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABackupAlarmAudioCurrent TEST.NEW TEST.NAME:getFPGABackupAlarmAudioCurrent.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.backupAlarmAudioPeakCurrent:4049 TEST.EXPECTED:FPGA.getFPGABackupAlarmAudioCurrent.return:395.41 TEST.END -- Subprogram: getFPGABloodLeakRxErrorCount -- Test Case: getFPGABloodLeakRxErrorCount.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodLeakRxErrorCount TEST.NEW TEST.NAME:getFPGABloodLeakRxErrorCount.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.END -- Subprogram: getFPGABloodLeakRxFIFOCount -- Test Case: getFPGABloodLeakRxFIFOCount.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodLeakRxFIFOCount TEST.NEW TEST.NAME:getFPGABloodLeakRxFIFOCount.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.END -- Subprogram: getFPGABloodLeakRxFIFODataOut -- Test Case: getFPGABloodLeakRxFIFODataOut.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodLeakRxFIFODataOut TEST.NEW TEST.NAME:getFPGABloodLeakRxFIFODataOut.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.END -- Subprogram: getFPGABloodLeakStatus -- Test Case: getFPGABloodLeakStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodLeakStatus TEST.NEW TEST.NAME:getFPGABloodLeakStatus.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x1000 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x1000 TEST.EXPECTED:FPGA.getFPGABloodLeakStatus.return:1 TEST.END -- Subprogram: getFPGABloodLeakTxFIFOCount -- Test Case: getFPGABloodLeakTxFIFOCount.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodLeakTxFIFOCount TEST.NEW TEST.NAME:getFPGABloodLeakTxFIFOCount.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.END -- Subprogram: getFPGABloodPumpHallSensorCount -- Test Case: getFPGABloodPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpHallSensorCount TEST.NEW TEST.NAME:getFPGABloodPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodPumpHallSensorCount:1234 TEST.EXPECTED:FPGA.getFPGABloodPumpHallSensorCount.return:1234 TEST.END -- Subprogram: getFPGABloodPumpHallSensorStatus -- Test Case: getFPGABloodPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGABloodPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodPumpHallSensorStatus:0x47 TEST.EXPECTED:FPGA.getFPGABloodPumpHallSensorStatus.return:0x47 TEST.END -- Subprogram: getFPGABloodPumpOcclusion -- Test Case: getFPGABloodPumpOcclusion_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpOcclusion TEST.NEW TEST.NAME:getFPGABloodPumpOcclusion_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodOcclusionData:400 TEST.EXPECTED:FPGA.getFPGABloodPumpOcclusion.return:400 TEST.END -- Subprogram: getFPGABloodPumpOcclusionErrorCounter -- Test Case: getFPGABloodPumpOcclusionErrorCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpOcclusionErrorCounter TEST.NEW TEST.NAME:getFPGABloodPumpOcclusionErrorCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodOcclusionErrorCount:12 TEST.EXPECTED:FPGA.getFPGABloodPumpOcclusionErrorCounter.return:12 TEST.END -- Subprogram: getFPGABloodPumpOcclusionReadCounter -- Test Case: getFPGABloodPumpOcclusionReadCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABloodPumpOcclusionReadCounter TEST.NEW TEST.NAME:getFPGABloodPumpOcclusionReadCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodOcclusionReadCount:45 TEST.EXPECTED:FPGA.getFPGABloodPumpOcclusionReadCounter.return:45 TEST.END -- Subprogram: getFPGABoardTemperature -- Test Case: getFPGABoardTemperature.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGABoardTemperature TEST.NEW TEST.NAME:getFPGABoardTemperature.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaTemperature:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.fpgaTemperature:0 TEST.END -- Subprogram: getFPGADVTArterialPressure -- Test Case: getFPGADVTArterialPressure.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADVTArterialPressure TEST.NEW TEST.NAME:getFPGADVTArterialPressure.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:100 TEST.EXPECTED:FPGA.getFPGADVTArterialPressure.return:100 TEST.END -- Subprogram: getFPGADVTArterialPressureReadCounter -- Test Case: getFPGADVTArterialPressureReadCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADVTArterialPressureReadCounter TEST.NEW TEST.NAME:getFPGADVTArterialPressureReadCounter.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressureReadCount:100 TEST.EXPECTED:FPGA.getFPGADVTArterialPressureReadCounter.return:100 TEST.END -- Subprogram: getFPGADVTArterialTemperature -- Test Case: getFPGADVTArterialTemperature.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADVTArterialTemperature TEST.NEW TEST.NAME:getFPGADVTArterialTemperature.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressureTemperature:100 TEST.EXPECTED:FPGA.getFPGADVTArterialTemperature.return:100 TEST.END -- Subprogram: getFPGADialInPumpHallSensorCount -- Test Case: getFPGADialInPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialInPumpHallSensorCount TEST.NEW TEST.NAME:getFPGADialInPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialInPumpHallSensorCount:2345 TEST.EXPECTED:FPGA.getFPGADialInPumpHallSensorCount.return:2345 TEST.END -- Subprogram: getFPGADialInPumpHallSensorStatus -- Test Case: getFPGADialInPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialInPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGADialInPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialInPumpHallSensorStatus:0x83 TEST.EXPECTED:FPGA.getFPGADialInPumpHallSensorStatus.return:0x83 TEST.END -- Subprogram: getFPGADialOutPumpHallSensorCount -- Test Case: getFPGADialOutPumpHallSensorCount_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialOutPumpHallSensorCount TEST.NEW TEST.NAME:getFPGADialOutPumpHallSensorCount_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialOutPumpHallSensorCount:0xD374 TEST.EXPECTED:FPGA.getFPGADialOutPumpHallSensorCount.return:0xD374 TEST.END -- Subprogram: getFPGADialOutPumpHallSensorStatus -- Test Case: getFPGADialOutPumpHallSensorStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADialOutPumpHallSensorStatus TEST.NEW TEST.NAME:getFPGADialOutPumpHallSensorStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialOutPumpSensorStatus:0xFA TEST.EXPECTED:FPGA.getFPGADialOutPumpHallSensorStatus.return:0xFA TEST.END -- Subprogram: getFPGAFrontDoorStatus -- Test Case: getFPGAFrontDoorStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAFrontDoorStatus TEST.NEW TEST.NAME:getFPGAFrontDoorStatus.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x10 TEST.EXPECTED:FPGA.getFPGAFrontDoorStatus.return:0x10 TEST.END -- Subprogram: getFPGAInletFan1TogglePeriod -- Test Case: getFPGAInletFan1TogglePeriod.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAInletFan1TogglePeriod TEST.NEW TEST.NAME:getFPGAInletFan1TogglePeriod.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fan1PulseTime:12 TEST.EXPECTED:FPGA.getFPGAInletFan1TogglePeriod.return:12 TEST.END -- Subprogram: getFPGAPBAADCTemperature -- Test Case: getFPGAPBAADCTemperature.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAPBAADCTemperature TEST.NEW TEST.NAME:getFPGAPBAADCTemperature.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1Channel1:1 TEST.EXPECTED:FPGA.getFPGAPBAADCTemperature.return:1 TEST.END -- Subprogram: getFPGAPumpTrackSwitchStatus -- Test Case: getFPGAPumpTrackSwitchStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAPumpTrackSwitchStatus TEST.NEW TEST.NAME:getFPGAPumpTrackSwitchStatus.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x20 TEST.EXPECTED:FPGA.getFPGAPumpTrackSwitchStatus.return:0x20 TEST.END -- Subprogram: getFPGASyringePumpADCChannel0 -- Test Case: getFPGASyringePumpADCChannel0.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCChannel0 TEST.NEW TEST.NAME:getFPGASyringePumpADCChannel0.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpAdcDataReadCh0:23 TEST.EXPECTED:FPGA.getFPGASyringePumpADCChannel0.return:23 TEST.END -- Subprogram: getFPGASyringePumpADCChannel1 -- Test Case: getFPGASyringePumpADCChannel1.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCChannel1 TEST.NEW TEST.NAME:getFPGASyringePumpADCChannel1.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpAdcDataReadCh1:56 TEST.EXPECTED:FPGA.getFPGASyringePumpADCChannel1.return:56 TEST.END -- Subprogram: getFPGASyringePumpADCChannel2 -- Test Case: getFPGASyringePumpADCChannel2.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCChannel2 TEST.NEW TEST.NAME:getFPGASyringePumpADCChannel2.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpAdcDataReadCh2:45 TEST.EXPECTED:FPGA.getFPGASyringePumpADCChannel2.return:45 TEST.END -- Subprogram: getFPGASyringePumpADCChannel3 -- Test Case: getFPGASyringePumpADCChannel3.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCChannel3 TEST.NEW TEST.NAME:getFPGASyringePumpADCChannel3.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpAdcDataReadCh3:12 TEST.EXPECTED:FPGA.getFPGASyringePumpADCChannel3.return:12 TEST.END -- Subprogram: getFPGASyringePumpADCReadCounter -- Test Case: getFPGASyringePumpADCReadCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCReadCounter TEST.NEW TEST.NAME:getFPGASyringePumpADCReadCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpADCReadCounter:24 TEST.EXPECTED:FPGA.getFPGASyringePumpADCReadCounter.return:24 TEST.END -- Subprogram: getFPGASyringePumpADCandDACStatus -- Test Case: getFPGASyringePumpADCandDACStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpADCandDACStatus TEST.NEW TEST.NAME:getFPGASyringePumpADCandDACStatus.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpADCandDACStatus:56 TEST.EXPECTED:FPGA.getFPGASyringePumpADCandDACStatus.return:56 TEST.END -- Subprogram: getFPGASyringePumpDACSetting -- Test Case: getFPGASyringePumpDACSetting.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpDACSetting TEST.NEW TEST.NAME:getFPGASyringePumpDACSetting.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.sPumpDACSet:10 TEST.VALUE:FPGA.getFPGASyringePumpDACSetting.return:1 TEST.EXPECTED:FPGA.getFPGASyringePumpDACSetting.return:10 TEST.END -- Subprogram: getFPGASyringePumpDACStatus -- Test Case: getFPGASyringePumpDACStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpDACStatus TEST.NEW TEST.NAME:getFPGASyringePumpDACStatus.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.sPumpDACRdStatus:1 TEST.VALUE:FPGA.getFPGASyringePumpDACStatus.return:0 TEST.EXPECTED:FPGA.getFPGASyringePumpDACStatus.return:1 TEST.END -- Subprogram: getFPGASyringePumpDACStoredSetting -- Test Case: getFPGASyringePumpDACStoredSetting.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpDACStoredSetting TEST.NEW TEST.NAME:getFPGASyringePumpDACStoredSetting.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.sPumpDACEEProm:10 TEST.EXPECTED:FPGA.getFPGASyringePumpDACStoredSetting.return:10 TEST.END -- Subprogram: getFPGASyringePumpEncoderPosition -- Test Case: getFPGASyringePumpEncoderPosition.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpEncoderPosition TEST.NEW TEST.NAME:getFPGASyringePumpEncoderPosition.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpEncPosition:5 TEST.EXPECTED:FPGA.getFPGASyringePumpEncoderPosition.return:5 TEST.END -- Subprogram: getFPGASyringePumpEncoderStatus -- Test Case: getFPGASyringePumpEncoderStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpEncoderStatus TEST.NEW TEST.NAME:getFPGASyringePumpEncoderStatus.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpEncoderStatus:6 TEST.EXPECTED:FPGA.getFPGASyringePumpEncoderStatus.return:6 TEST.END -- Subprogram: getFPGASyringePumpStatus -- Test Case: getFPGASyringePumpStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGASyringePumpStatus TEST.NEW TEST.NAME:getFPGASyringePumpStatus.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.syringePumpStatus:1 TEST.EXPECTED:FPGA.getFPGASyringePumpStatus.return:1 TEST.END -- Subprogram: getFPGATDVTArterialPressureErrorCounter -- Test Case: getFPGATDVTArterialPressureErrorCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGATDVTArterialPressureErrorCounter TEST.NEW TEST.NAME:getFPGATDVTArterialPressureErrorCounter.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.END -- Subprogram: getFPGATemperature -- Test Case: getFPGATemperature.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGATemperature TEST.NEW TEST.NAME:getFPGATemperature.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaTemperature:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.fpgaTemperature:0 TEST.END -- Subprogram: getFPGATimerCount -- Test Case: getFPGATimerCount.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGATimerCount TEST.NEW TEST.NAME:getFPGATimerCount.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaTimerCount_ms:1 TEST.EXPECTED:FPGA.getFPGATimerCount.return:1 TEST.END -- Subprogram: getFPGAValveBloodArterialCurrentCounts -- Test Case: getFPGAValveBloodArterialCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodArterialCurrentCounts TEST.NEW TEST.NAME:getFPGAValveBloodArterialCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBACurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodArterialCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodArterialCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodArterialPosition -- Test Case: getFPGAValveBloodArterialPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodArterialPosition TEST.NEW TEST.NAME:getFPGAValveBloodArterialPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBAPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodArterialPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodArterialPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodVenousCurrentCounts -- Test Case: getFPGAValveBloodVenousCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodVenousCurrentCounts TEST.NEW TEST.NAME:getFPGAValveBloodVenousCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBVCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodVenousCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodVenousCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveBloodVenousPosition -- Test Case: getFPGAValveBloodVenousPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveBloodVenousPosition TEST.NEW TEST.NAME:getFPGAValveBloodVenousPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VBVPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveBloodVenousPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveBloodVenousPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerInletCurrentCounts -- Test Case: getFPGAValveDialyzerInletCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerInletCurrentCounts TEST.NEW TEST.NAME:getFPGAValveDialyzerInletCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDiCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerInletCurrentCounts.return:0x800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerInletCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerInletPosition -- Test Case: getFPGAValveDialyzerInletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerInletPosition TEST.NEW TEST.NAME:getFPGAValveDialyzerInletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDiPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerInletPosition.return:01440 TEST.EXPECTED:FPGA.getFPGAValveDialyzerInletPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerOutletCurrentCounts -- Test Case: getFPGAValveDialyzerOutletCurrentCounts_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerOutletCurrentCounts TEST.NEW TEST.NAME:getFPGAValveDialyzerOutletCurrentCounts_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDoCurrent:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerOutletCurrentCounts.return:800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerOutletCurrentCounts.return:0x1234 TEST.END -- Subprogram: getFPGAValveDialyzerOutletPosition -- Test Case: getFPGAValveDialyzerOutletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValveDialyzerOutletPosition TEST.NEW TEST.NAME:getFPGAValveDialyzerOutletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.VDoPosition:0x1234 TEST.VALUE:FPGA.getFPGAValveDialyzerOutletPosition.return:800 TEST.EXPECTED:FPGA.getFPGAValveDialyzerOutletPosition.return:0x1234 TEST.END -- Subprogram: getFPGAValvesStatus -- Test Case: getFPGAValvesStatus_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAValvesStatus TEST.NEW TEST.NAME:getFPGAValvesStatus_NominalPath TEST.VALUE:FPGA.<>.fpgaSensorReadings.valveStatus:0x1234 TEST.VALUE:FPGA.getFPGAValvesStatus.return:34 TEST.EXPECTED:FPGA.getFPGAValvesStatus.return:0x1234 TEST.END -- Subprogram: getFPGAVcc -- Test Case: getFPGAVcc.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVcc TEST.NEW TEST.NAME:getFPGAVcc.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaIntVoltage:1 TEST.EXPECTED:FPGA.getFPGAVcc.return:0.000732422 TEST.END -- Subprogram: getFPGAVccAux -- Test Case: getFPGAVccAux.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVccAux TEST.NEW TEST.NAME:getFPGAVccAux.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaAuxVoltage:1 TEST.EXPECTED:FPGA.getFPGAVccAux.return:0.000732422 TEST.END -- Subprogram: getFPGAVenousPressure -- Test Case: getFPGAVenousPressure_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVenousPressure TEST.NEW TEST.NAME:getFPGAVenousPressure_NominalPath TEST.EXPECTED:FPGA.getFPGAVenousPressure.return:0 TEST.END -- Subprogram: getFPGAVenousPressureErrorCounter -- Test Case: getFPGAVenousPressureErrorCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVenousPressureErrorCounter TEST.NEW TEST.NAME:getFPGAVenousPressureErrorCounter.001 TEST.BASIS_PATH:1 of 1 TEST.NOTES: No branches in subprogram TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaSensorReadings.VenousErrorCounter:10 TEST.EXPECTED:FPGA.getFPGAVenousPressureErrorCounter.return:10 TEST.END -- Subprogram: getFPGAVenousPressureReadCounter -- Test Case: getFPGAVenousPressureReadCounter.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVenousPressureReadCounter TEST.NEW TEST.NAME:getFPGAVenousPressureReadCounter.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousReadCounter:2 TEST.EXPECTED:FPGA.getFPGAVenousPressureReadCounter.return:2 TEST.END -- Subprogram: getFPGAVenousPressureTemperature -- Test Case: getFPGAVenousPressureTemperature.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVenousPressureTemperature TEST.NEW TEST.NAME:getFPGAVenousPressureTemperature.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousTemperature:45 TEST.EXPECTED:FPGA.getFPGAVenousPressureTemperature.return:45 TEST.END -- Subprogram: getFPGAVersions -- Test Case: getFPGAVersions_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVersions TEST.NEW TEST.NAME:getFPGAVersions_NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x5A TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:2 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRevMajor:1 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRevLab:3 TEST.VALUE:FPGA.getFPGAVersions.Id:<> TEST.VALUE:FPGA.getFPGAVersions.Maj:<> TEST.VALUE:FPGA.getFPGAVersions.Min:<> TEST.VALUE:FPGA.getFPGAVersions.Lab:<> TEST.EXPECTED:FPGA.getFPGAVersions.Id[0]:0x5A TEST.EXPECTED:FPGA.getFPGAVersions.Maj[0]:1 TEST.EXPECTED:FPGA.getFPGAVersions.Min[0]:2 TEST.EXPECTED:FPGA.getFPGAVersions.Lab[0]:3 TEST.END -- Subprogram: getFPGAVpvn -- Test Case: getFPGAVpvn.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAVpvn TEST.NEW TEST.NAME:getFPGAVpvn.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaVpvn:1 TEST.EXPECTED:FPGA.getFPGAVpvn.return:0.000244141 TEST.END -- Subprogram: handleFPGAReadHeaderState -- Test Case: NominalCase TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReadHeaderState TEST.NEW TEST.NAME:NominalCase TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.handleFPGAReadHeaderState.return:FPGA_STATE_RCV_HEADER TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]::EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[5]::EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[6]::EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Subprogram: handleFPGAReceiveAllSensorsState -- Test Case: BadCRC TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:BadCRC TEST.IMPORT_FAILURES: (E) @LINE: 1610 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1623 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[127]:0x11 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[128]:0x34 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[0]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[4]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[5]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[6]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[7]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.END -- Test Case: NAKResponse TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NAKResponse TEST.IMPORT_FAILURES: (E) @LINE: 1712 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1718 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 598 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 599 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 600 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 601 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 602 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 603 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 604 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 605 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 606 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 >>> (E) @LINE: 611 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 612 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 613 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 614 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 615 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 616 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 617 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 618 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 619 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xEF TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.END -- Test Case: NoResponseReceived TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NoResponseReceived TEST.IMPORT_FAILURES: (E) @LINE: 1787 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1792 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 633 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 634 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 635 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 636 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 637 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 638 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 639 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 640 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 641 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 >>> (E) @LINE: 646 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 647 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 648 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 649 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 650 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 651 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 652 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 653 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 654 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Test Case: NoWriteResponseReceived TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NoWriteResponseReceived TEST.IMPORT_FAILURES: (E) @LINE: 1862 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1867 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:2 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 669 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 670 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 671 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 672 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 673 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 674 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 675 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 676 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 677 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 >>> (E) @LINE: 682 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 683 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 684 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 685 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 686 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 687 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 688 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 689 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 690 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0x0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Test Case: NoWriteResponseReceived2 TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NoWriteResponseReceived2 TEST.IMPORT_FAILURES: (E) @LINE: 1880 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1885 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:2 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Test Case: NoWriteResponseReceived3 TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NoWriteResponseReceived3 TEST.IMPORT_FAILURES: (E) @LINE: 1898 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 1903 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:2 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0x0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NominalPath TEST.IMPORT_FAILURES: (E) @LINE: 1979 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 2202 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDataPktCount:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterDataPktCount >>> (E) @LINE: 2203 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSlowPktCounts:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSlowPktCounts >>> (E) @LINE: 740 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 741 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 742 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 743 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 744 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 745 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 746 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 747 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 748 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 >>> (E) @LINE: 753 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0x201 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodLeak >>> (E) @LINE: 754 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0x6050403 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1b >>> (E) @LINE: 755 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0x90807 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2b >>> (E) @LINE: 756 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0x4030201 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp1 >>> (E) @LINE: 757 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0x8070605 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: venousPressure >>> (E) @LINE: 758 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0x2010009 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: arterialPressure >>> (E) @LINE: 759 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0x6050403 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc1a >>> (E) @LINE: 760 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0x90807 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: adc2a >>> (E) @LINE: 761 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0x4030201 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateTemp2 TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[163]:0x12 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[164]:0x34 TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountProcessor:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.errorCountPC:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[0]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[4]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[5]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[6]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[7]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[127]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[128]:INPUT_BASE=16 TEST.END -- Test Case: handleFPGAReceiveAllSensorsState.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:handleFPGAReceiveAllSensorsState.001 TEST.IMPORT_FAILURES: (E) @LINE: 2040 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored TEST.END_IMPORT_FAILURES: TEST.MCDC_BASIS_PATH:7 of 9 TEST.NOTES: This is an automatically generated test case. Test Path 7 (1) if ((0) == fpgaWriteCommandResponseReceived || fpgaWriteResponseBuffer[0] != 0xa5) ==> FALSE (2) if ((1) == fpgaReadCommandResponseReceived) ==> TRUE (3) if (fpgaReadResponseBuffer[0] == 0xaa) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #3, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:165 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:170 TEST.END -- Subprogram: handleFPGAReceiveHeaderState -- Test Case: BadCRC TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveHeaderState TEST.NEW TEST.NAME:BadCRC TEST.IMPORT_FAILURES: (E) @LINE: 2060 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 2081 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 1247 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1255 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:0x2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:0x5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:0x6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:0x7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:0x8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0x1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[11]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[12]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[13]:4 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaStatus:0x0 TEST.EXPECTED:FPGA.handleFPGAReceiveHeaderState.return:FPGA_STATE_READ_HEADER TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[0]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[4]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[5]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[6]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[7]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteResponseBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[17]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[18]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[127]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[128]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[163]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[164]:INPUT_BASE=16 TEST.END -- Test Case: NAKResponse TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveHeaderState TEST.NEW TEST.NAME:NAKResponse TEST.IMPORT_FAILURES: (E) @LINE: 2123 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 2140 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 1282 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1289 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xFA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaStatus:0x0 TEST.EXPECTED:FPGA.handleFPGAReceiveHeaderState.return:FPGA_STATE_READ_HEADER TEST.END -- Test Case: NoResponseReceived TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveHeaderState TEST.NEW TEST.NAME:NoResponseReceived TEST.IMPORT_FAILURES: (E) @LINE: 2163 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) @LINE: 2180 TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 1315 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1322 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0x0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaStatus:0x0 TEST.EXPECTED:FPGA.handleFPGAReceiveHeaderState.return:FPGA_STATE_READ_HEADER TEST.END -- Test Case: NominalCase TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveHeaderState TEST.NEW TEST.NAME:NominalCase TEST.IMPORT_FAILURES: (E) @LINE: 2203 TEST.VALUE:FPGA.<>.fpgaCommRetryCount:1 >>> Unknown parameter/object name fpgaCommRetryCount >>> Value Line Error - Command Ignored (E) Errors from previous script import(s) >>> (E) @LINE: 1348 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1356 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x403 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:0x8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:0x6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:0x12 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:0x34 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteCmdBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[0]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[4]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[5]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[6]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadCmdBuffer[7]:EXPECTED_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaWriteResponseBuffer[0]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[1]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[2]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[5]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[6]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[7]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[8]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[9]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[10]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[35]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[36]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[40]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[41]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[59]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[60]::INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[127]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[128]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[163]:INPUT_BASE=16 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[164]:INPUT_BASE=16 TEST.END -- Test Case: handleFPGAReceiveHeaderState.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveHeaderState TEST.NEW TEST.NAME:handleFPGAReceiveHeaderState.001 TEST.MCDC_BASIS_PATH:4 of 6 TEST.NOTES: This is an automatically generated test case. Test Path 4 (1) if ((1) == fpgaReadCommandResponseReceived) ==> TRUE (2) if (fpgaReadResponseBuffer[0] == 0xaa) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #2, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:170 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[0]:170 TEST.END -- Subprogram: handleFPGAWriteAllActuatorsState -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAWriteAllActuatorsState TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234,0x5678 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[0]:0x55 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[4]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[5]:0x0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:1 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x56 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x78 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:5 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.handleFPGAWriteAllActuatorsState.return:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.type:(2)0 TEST.ATTRIBUTES:FPGA.<>.fpgaReadResponseBuffer[0]:INPUT_BASE=16 TEST.END -- Subprogram: initFPGA -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:initFPGA TEST.NEW TEST.NAME:NominalPath TEST.IMPORT_FAILURES: (E) Errors from previous script import(s) >>> (E) @LINE: 2808 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowLast:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowLast >>> (E) @LINE: 2809 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterDeviceStatus >>> (E) @LINE: 2810 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowLast:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowLast >>> (E) @LINE: 2811 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterDeviceStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterDeviceStatus >>> (E) @LINE: 2895 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowLast:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowLast >>> (E) @LINE: 2896 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterDeviceStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterDeviceStatus >>> (E) @LINE: 2897 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowLast:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowLast >>> (E) @LINE: 2898 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterDeviceStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterDeviceStatus >>> (E) @LINE: 1593 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:1 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1599 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.bloodValveSetState:1 >>> >>> Expected a field name from the record type FPGA_ACTUATORS_T >>> >>> Read: bloodValveSetState >>> (E) @LINE: 1682 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1688 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.bloodValveSetState:0 >>> >>> Expected a field name from the record type FPGA_ACTUATORS_T >>> >>> Read: bloodValveSetState >>> (E) @LINE: 1330 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterCommStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterCommStatus >>> (E) @LINE: 1331 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterFrameCount:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterFrameCount >>> (E) @LINE: 1334 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowAvg:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowAvg >>> (E) @LINE: 1335 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSoundSpeed:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSoundSpeed >>> (E) @LINE: 1336 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterAccFlowData:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterAccFlowData >>> (E) @LINE: 1337 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSignalStrength:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSignalStrength >>> (E) @LINE: 1338 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSensorID:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSensorID >>> (E) @LINE: 1339 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterCommStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterCommStatus >>> (E) @LINE: 1340 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterFrameCount:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterFrameCount >>> (E) @LINE: 1343 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowAvg:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowAvg >>> (E) @LINE: 1344 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSoundSpeed:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSoundSpeed >>> (E) @LINE: 1345 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterAccFlowData:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterAccFlowData >>> (E) @LINE: 1346 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSignalStrength:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSignalStrength >>> (E) @LINE: 1347 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSensorID:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSensorID >>> (E) @LINE: 1433 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterCommStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterCommStatus >>> (E) @LINE: 1434 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterFrameCount:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterFrameCount >>> (E) @LINE: 1437 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowAvg:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowAvg >>> (E) @LINE: 1438 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSoundSpeed:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSoundSpeed >>> (E) @LINE: 1439 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterAccFlowData:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterAccFlowData >>> (E) @LINE: 1440 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSignalStrength:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSignalStrength >>> (E) @LINE: 1441 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSensorID:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSensorID >>> (E) @LINE: 1442 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterCommStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterCommStatus >>> (E) @LINE: 1443 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterFrameCount:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterFrameCount >>> (E) @LINE: 1446 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowAvg:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowAvg >>> (E) @LINE: 1447 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSoundSpeed:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSoundSpeed >>> (E) @LINE: 1448 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterAccFlowData:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterAccFlowData >>> (E) @LINE: 1449 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSignalStrength:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSignalStrength >>> (E) @LINE: 1450 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSensorID:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSensorID >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1599 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.bloodValveSetState:1 >>> >>> Expected a field name from the record type FPGA_ACTUATORS_T >>> >>> Read: bloodValveSetState >>> (E) @LINE: 1682 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0 >>> >>> Expected a field name from the record type FPGA_HEADER_T >>> >>> Read: fpgaControl >>> (E) @LINE: 1688 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.bloodValveSetState:0 >>> >>> Expected a field name from the record type FPGA_ACTUATORS_T >>> >>> Read: bloodValveSetState >>> (E) @LINE: 1330 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterCommStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterCommStatus >>> (E) @LINE: 1331 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterFrameCount:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterFrameCount >>> (E) @LINE: 1334 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowAvg:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowAvg >>> (E) @LINE: 1335 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSoundSpeed:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSoundSpeed >>> (E) @LINE: 1336 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterAccFlowData:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterAccFlowData >>> (E) @LINE: 1337 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSignalStrength:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSignalStrength >>> (E) @LINE: 1338 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSensorID:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSensorID >>> (E) @LINE: 1339 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterCommStatus:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterCommStatus >>> (E) @LINE: 1340 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterFrameCount:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterFrameCount >>> (E) @LINE: 1343 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowAvg:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowAvg >>> (E) @LINE: 1344 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSoundSpeed:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSoundSpeed >>> (E) @LINE: 1345 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterAccFlowData:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterAccFlowData >>> (E) @LINE: 1346 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSignalStrength:1.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSignalStrength >>> (E) @LINE: 1347 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSensorID:1 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSensorID >>> (E) @LINE: 1433 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterCommStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterCommStatus >>> (E) @LINE: 1434 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterFrameCount:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterFrameCount >>> (E) @LINE: 1437 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowAvg:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowAvg >>> (E) @LINE: 1438 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSoundSpeed:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSoundSpeed >>> (E) @LINE: 1439 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterAccFlowData:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterAccFlowData >>> (E) @LINE: 1440 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSignalStrength:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSignalStrength >>> (E) @LINE: 1441 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodFlowMeterSensorID:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: bloodFlowMeterSensorID >>> (E) @LINE: 1442 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterCommStatus:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterCommStatus >>> (E) @LINE: 1443 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterFrameCount:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterFrameCount >>> (E) @LINE: 1446 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowAvg:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowAvg >>> (E) @LINE: 1447 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSoundSpeed:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSoundSpeed >>> (E) @LINE: 1448 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterAccFlowData:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterAccFlowData >>> (E) @LINE: 1449 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSignalStrength:0.0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSignalStrength >>> (E) @LINE: 1450 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateFlowMeterSensorID:0 >>> >>> Expected a field name from the record type FPGA_SENSORS_T >>> >>> Read: dialysateFlowMeterSensorID TEST.END_IMPORT_FAILURES: TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[0]:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[2]:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[4]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[2]:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[4]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.DADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.CHCTRL:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.PORTASGN:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.WRSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.TTYPE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODERD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODEWR:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.AUTOINIT:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.DADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.CHCTRL:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.PORTASGN:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.WRSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.TTYPE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODERD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODEWR:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.AUTOINIT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.DADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.CHCTRL:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.PORTASGN:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.WRSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.TTYPE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ADDMODERD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ADDMODEWR:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.AUTOINIT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.DADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.CHCTRL:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELCNT:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRDOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRSOFFSET:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.PORTASGN:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.WRSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.TTYPE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODERD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODEWR:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.AUTOINIT:1 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:1 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:1 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[0]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[3]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer[4]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteResponseBuffer[0]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteResponseBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteResponseBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteResponseBuffer[3]:0 TEST.EXPECTED:FPGA.<>.fpgaWriteResponseBuffer[4]:0 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[0]:0 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[3]:0 TEST.EXPECTED:FPGA.<>.fpgaReadResponseBuffer[4]:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.DADD:0xFFF7E438 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.CHCTRL:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.ELCNT:1 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.ELDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.ELSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.FRDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.FRSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.PORTASGN:4 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.RDSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.WRSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.TTYPE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODERD:1 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODEWR:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.AUTOINIT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.SADD:0xFFF7E434 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.CHCTRL:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.ELCNT:1 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.ELDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.ELSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.PORTASGN:4 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.RDSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.WRSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.TTYPE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODERD:0 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODEWR:1 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.AUTOINIT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.DADD:0xFFF7E438 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.CHCTRL:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.ELCNT:1 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.ELDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.ELSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.PORTASGN:4 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.RDSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.WRSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.TTYPE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.ADDMODERD:1 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.ADDMODEWR:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.AUTOINIT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.SADD:0xFFF7E434 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.CHCTRL:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.ELCNT:1 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.ELDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.ELSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRDOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRSOFFSET:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.PORTASGN:4 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.RDSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.WRSIZE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.TTYPE:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODERD:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODEWR:1 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.AUTOINIT:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaStatus:0 TEST.EXPECTED:uut_prototype_stubs.sciEnableNotification.flags:0x6000000 TEST.EXPECTED:uut_prototype_stubs.dmaReqAssign.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaReqAssign.reqline:28,29 TEST.EXPECTED:uut_prototype_stubs.dmaSetPriority.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaSetPriority.priority:HIGHPRIORITY,LOWPRIORITY TEST.EXPECTED:uut_prototype_stubs.dmaEnableInterrupt.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaEnableInterrupt.inttype:(2)BTC TEST.END -- Subprogram: monitorFPGAPowerStatus -- Test Case: monitorFPGAPowerStatus.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:monitorFPGAPowerStatus TEST.NEW TEST.NAME:monitorFPGAPowerStatus.001 TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_START TEST.END -- Subprogram: noFPGABubbleDetected -- Test Case: noFPGABubbleDetected.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:noFPGABubbleDetected TEST.NEW TEST.NAME:noFPGABubbleDetected.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:1 TEST.VALUE:FPGA.noFPGABubbleDetected.bubble:0 TEST.EXPECTED:FPGA.noFPGABubbleDetected.return:0 TEST.END -- Test Case: noFPGABubbleDetected.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:noFPGABubbleDetected TEST.NEW TEST.NAME:noFPGABubbleDetected.002 TEST.MCDC_BASIS_PATH:1 of 6 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (bubble == (ADA)) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #1, subcondition "a". Condition a ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.noFPGABubbleDetected.bubble:1 TEST.EXPECTED:FPGA.noFPGABubbleDetected.return:0 TEST.END -- Test Case: noFPGABubbleDetected.003 TEST.UNIT:FPGA TEST.SUBPROGRAM:noFPGABubbleDetected TEST.NEW TEST.NAME:noFPGABubbleDetected.003 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x2 TEST.VALUE:FPGA.noFPGABubbleDetected.bubble:0 TEST.EXPECTED:FPGA.noFPGABubbleDetected.return:1 TEST.END -- Subprogram: noFPGAFluidLeakDetected -- Test Case: noFPGAFluidLeakDetected.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:noFPGAFluidLeakDetected TEST.NEW TEST.NAME:noFPGAFluidLeakDetected.001 TEST.VALUE:FPGA.<>.fpgaSensorReadings.fpgaGPIO:0x40 TEST.EXPECTED:FPGA.noFPGAFluidLeakDetected.return:1 TEST.END -- Test Case: noFPGAFluidLeakDetected.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:noFPGAFluidLeakDetected TEST.NEW TEST.NAME:noFPGAFluidLeakDetected.002 TEST.MCDC_BASIS_PATH:1 of 2 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) (0 == noFPGAFluidLeakDetected) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #1, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: Cannot set local variable noFPGAFluidLeakDetected in branch 1 TEST.END_NOTES: TEST.EXPECTED:FPGA.noFPGAFluidLeakDetected.return:0 TEST.END -- Subprogram: resetFPGACommFlags -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:resetFPGACommFlags TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Subprogram: setAlarmAudioState -- Test Case: setAlarmAudioState.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setAlarmAudioState TEST.NEW TEST.NAME:setAlarmAudioState.001 TEST.MCDC_BASIS_PATH:2 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 2 (1) if (state <= (NUM_OF_ALARM_PRIORITIES) && volumeLevel <= (4)) ==> TRUE Row number 1 forms a pair with Row 3 for Condition #1, subcondition "a". Condition a ==> TRUE Condition b ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.setAlarmAudioState.state:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeLevel:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeDivider:<> TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.alarmControl:0 TEST.END -- Test Case: setAlarmAudioState.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:setAlarmAudioState TEST.NEW TEST.NAME:setAlarmAudioState.002 TEST.MCDC_BASIS_PATH:3 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 3 (1) if (state <= (NUM_OF_ALARM_PRIORITIES) && volumeLevel <= (4)) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #1, subcondition "b". Condition a ==> TRUE Condition b ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.setAlarmAudioState.state:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeLevel:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeDivider:<> TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.alarmControl:3 TEST.END -- Test Case: setAlarmAudioState.003 TEST.UNIT:FPGA TEST.SUBPROGRAM:setAlarmAudioState TEST.NEW TEST.NAME:setAlarmAudioState.003 TEST.MCDC_BASIS_PATH:1 of 3 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (state <= (NUM_OF_ALARM_PRIORITIES) && volumeLevel <= (4)) ==> FALSE Row number 3 forms a pair with Row 1 for Condition #1, subcondition "a". Condition a ==> FALSE Condition b ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.setAlarmAudioState.state:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeLevel:<> TEST.VALUE:FPGA.setAlarmAudioState.volumeDivider:<> TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.alarmControl:3 TEST.END -- Subprogram: setFPGABloodLeakUARTControl -- Test Case: setFPGABloodLeakUARTControl.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGABloodLeakUARTControl TEST.NEW TEST.NAME:setFPGABloodLeakUARTControl.001 TEST.VALUE:FPGA.setFPGABloodLeakUARTControl.value:1 TEST.EXPECTED:FPGA.setFPGABloodLeakUARTControl.value:1 TEST.END -- Subprogram: setFPGABloodLeakUARTTransmit -- Test Case: setFPGABloodLeakUARTTransmit.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGABloodLeakUARTTransmit TEST.NEW TEST.NAME:setFPGABloodLeakUARTTransmit.001 TEST.VALUE:FPGA.setFPGABloodLeakUARTTransmit.value:12 TEST.EXPECTED:FPGA.setFPGABloodLeakUARTTransmit.value:12 TEST.END -- Subprogram: setFPGABubbleSelfTest -- Test Case: setFPGABubbleSelfTest.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGABubbleSelfTest TEST.NEW TEST.NAME:setFPGABubbleSelfTest.001 TEST.MCDC_BASIS_PATH:2 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 2 (1) if (bubble == (ADA)) ==> TRUE Row number 1 forms a pair with Row 2 for Condition #1, subcondition "a". Condition a ==> TRUE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.setFPGABubbleSelfTest.bubble:0 TEST.EXPECTED:FPGA.setFPGABubbleSelfTest.bubble:0 TEST.END -- Test Case: setFPGABubbleSelfTest.002 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGABubbleSelfTest TEST.NEW TEST.NAME:setFPGABubbleSelfTest.002 TEST.MCDC_BASIS_PATH:1 of 4 TEST.NOTES: This is an automatically generated test case. Test Path 1 (1) if (bubble == (ADA)) ==> FALSE Row number 2 forms a pair with Row 1 for Condition #1, subcondition "a". Condition a ==> FALSE Test Case Generation Notes: TEST.END_NOTES: TEST.VALUE:FPGA.setFPGABubbleSelfTest.bubble:1 TEST.EXPECTED:FPGA.setFPGABubbleSelfTest.bubble:1 TEST.END -- Subprogram: setFPGASyringePumpADCandDACControlFlags -- Test Case: setFPGASyringePumpADCandDACControlFlags.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGASyringePumpADCandDACControlFlags TEST.NEW TEST.NAME:setFPGASyringePumpADCandDACControlFlags.001 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.syringePumpADCandDACControl:1 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.syringePumpADCandDACControl:0 TEST.END -- Subprogram: setFPGASyringePumpControlFlags -- Test Case: setFPGASyringePumpControlFlags.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGASyringePumpControlFlags TEST.NEW TEST.NAME:setFPGASyringePumpControlFlags.001 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.syringePumpControl:1 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.syringePumpControl:0 TEST.END -- Subprogram: setFPGASyringePumpDACOutputLevel -- Test Case: setFPGASyringePumpDACOutputLevel.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGASyringePumpDACOutputLevel TEST.NEW TEST.NAME:setFPGASyringePumpDACOutputLevel.001 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.syringePumpDACOut:0 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.syringePumpDACOut:0 TEST.END -- Subprogram: setFPGASyringePumpStepToggleTime -- Test Case: setFPGASyringePumpStepToggleTime.001 TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGASyringePumpStepToggleTime TEST.NEW TEST.NAME:setFPGASyringePumpStepToggleTime.001 TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.syringePumpStepToggleTime:12 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.syringePumpStepToggleTime:0 TEST.END -- Subprogram: setFPGAValveBloodArterialPosition -- Test Case: setFPGAValveBloodArterialPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGAValveBloodArterialPosition TEST.NEW TEST.NAME:setFPGAValveBloodArterialPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.VBASetPoint:800 TEST.VALUE:FPGA.setFPGAValveBloodArterialPosition.setPoint:0x1234 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.VBASetPoint:0x1234 TEST.END -- Subprogram: setFPGAValveBloodVenousPosition -- Test Case: setFPGAValveBloodVenousPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGAValveBloodVenousPosition TEST.NEW TEST.NAME:setFPGAValveBloodVenousPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.VBVSetPoint:800 TEST.VALUE:FPGA.setFPGAValveBloodVenousPosition.setPoint:0x1234 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.VBVSetPoint:0x1234 TEST.END -- Subprogram: setFPGAValveDialyzerInletPosition -- Test Case: setFPGAValveDialyzerInletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGAValveDialyzerInletPosition TEST.NEW TEST.NAME:setFPGAValveDialyzerInletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.VDiSetPoint:800 TEST.VALUE:FPGA.setFPGAValveDialyzerInletPosition.setPoint:0x1234 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.VDiSetPoint:0x1234 TEST.END -- Subprogram: setFPGAValveDialyzerOutletPosition -- Test Case: setFPGAValveDialyzerOutletPosition_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGAValveDialyzerOutletPosition TEST.NEW TEST.NAME:setFPGAValveDialyzerOutletPosition_NominalPath TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.VDoSetPoint:800 TEST.VALUE:FPGA.setFPGAValveDialyzerOutletPosition.setPoint:0x1234 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.VDoSetPoint:0x1234 TEST.END -- Subprogram: setFPGAValvesControlMode -- Test Case: setFPGAValvesControlMode_NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setFPGAValvesControlMode TEST.NEW TEST.NAME:setFPGAValvesControlMode_NominalPath TEST.VALUE:FPGA.<>.fpgaActuatorSetPoints.fpgaPIDControl:78 TEST.VALUE:FPGA.setFPGAValvesControlMode.bits:0x1234 TEST.EXPECTED:FPGA.<>.fpgaActuatorSetPoints.fpgaPIDControl:0x1234 TEST.END -- Subprogram: setupDMAForReadCmd -- Test Case: LengthTooLarge TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForReadCmd TEST.NEW TEST.NAME:LengthTooLarge TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForReadCmd.bytes2Transmit:9 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.END -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForReadCmd TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForReadCmd.bytes2Transmit:8 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:8 TEST.END -- Subprogram: setupDMAForReadResp -- Test Case: LengthTooLarge TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForReadResp TEST.NEW TEST.NAME:LengthTooLarge TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForReadResp.bytes2Receive:265 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.END -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForReadResp TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForReadResp.bytes2Receive:264 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:264 TEST.END -- Subprogram: setupDMAForWriteCmd -- Test Case: LengthTooLarge TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForWriteCmd TEST.NEW TEST.NAME:LengthTooLarge TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForWriteCmd.bytes2Transmit:265 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:0 TEST.END -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForWriteCmd TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForWriteCmd.bytes2Transmit:264 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:264 TEST.END -- Subprogram: setupDMAForWriteResp -- Test Case: LengthTooLarge TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForWriteResp TEST.NEW TEST.NAME:LengthTooLarge TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForWriteResp.bytes2Receive:9 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:0 TEST.END -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:setupDMAForWriteResp TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:0 TEST.VALUE:FPGA.setupDMAForWriteResp.bytes2Receive:8 TEST.EXPECTED:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:8 TEST.END -- Subprogram: signalFPGAReceiptCompleted -- Test Case: BulkWriteAndReadInProgressAfterWrite TEST.UNIT:FPGA TEST.SUBPROGRAM:signalFPGAReceiptCompleted TEST.NEW TEST.NAME:BulkWriteAndReadInProgressAfterWrite TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:1 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:0,2 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:0,2 TEST.END -- Test Case: NothingInProgress TEST.UNIT:FPGA TEST.SUBPROGRAM:signalFPGAReceiptCompleted TEST.NEW TEST.NAME:NothingInProgress TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:1 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: ReadCmdInProgress TEST.UNIT:FPGA TEST.SUBPROGRAM:signalFPGAReceiptCompleted TEST.NEW TEST.NAME:ReadCmdInProgress TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:1 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.END -- Test Case: WriteCmdInProgress TEST.UNIT:FPGA TEST.SUBPROGRAM:signalFPGAReceiptCompleted TEST.NEW TEST.NAME:WriteCmdInProgress TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:1 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Subprogram: signalFPGATransmitCompleted -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:signalFPGATransmitCompleted TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Subprogram: startDMAReadCmd -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:startDMAReadCmd TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.DADD:2 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.CHCTRL:3 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:4 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELCNT:5 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELDOFFSET:6 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ELSOFFSET:7 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRDOFFSET:8 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRSOFFSET:9 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.PORTASGN:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.WRSIZE:2 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.TTYPE:3 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ADDMODERD:4 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.ADDMODEWR:5 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.AUTOINIT:6 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.SADD:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.DADD:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.CHCTRL:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRCNT:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELCNT:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELDOFFSET:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELSOFFSET:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRDOFFSET:8 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRSOFFSET:9 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.PORTASGN:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.RDSIZE:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.WRSIZE:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.TTYPE:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODERD:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODEWR:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.AUTOINIT:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.type:0 TEST.END -- Subprogram: startDMAReceiptOfReadResp -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:startDMAReceiptOfReadResp TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.DADD:2 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.CHCTRL:3 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:4 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELCNT:5 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELDOFFSET:6 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ELSOFFSET:7 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRDOFFSET:8 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRSOFFSET:9 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.PORTASGN:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.WRSIZE:2 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.TTYPE:3 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODERD:4 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.ADDMODEWR:5 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.AUTOINIT:6 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.SADD:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.DADD:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.CHCTRL:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRCNT:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELCNT:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELDOFFSET:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELSOFFSET:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRDOFFSET:8 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRSOFFSET:9 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.PORTASGN:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.RDSIZE:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.WRSIZE:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.TTYPE:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODERD:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODEWR:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.AUTOINIT:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.type:0 TEST.END -- Subprogram: startDMAReceiptOfWriteResp -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:startDMAReceiptOfWriteResp TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.DADD:2 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.CHCTRL:3 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRCNT:4 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELCNT:5 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELDOFFSET:6 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ELSOFFSET:7 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRDOFFSET:8 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.FRSOFFSET:9 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.PORTASGN:0 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.WRSIZE:2 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.TTYPE:3 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODERD:4 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.ADDMODEWR:5 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.AUTOINIT:6 TEST.VALUE:FPGA.<>.fpgaDMAWriteRespControlRecord.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.SADD:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.DADD:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.CHCTRL:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRCNT:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELCNT:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELDOFFSET:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELSOFFSET:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRDOFFSET:8 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRSOFFSET:9 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.PORTASGN:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.RDSIZE:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.WRSIZE:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.TTYPE:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODERD:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODEWR:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.AUTOINIT:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.type:0 TEST.END -- Subprogram: startDMAWriteCmd -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:startDMAWriteCmd TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.SADD:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.DADD:2 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.CHCTRL:3 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRCNT:4 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELCNT:5 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELDOFFSET:6 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ELSOFFSET:7 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRDOFFSET:8 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.FRSOFFSET:9 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.PORTASGN:0 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.RDSIZE:1 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.WRSIZE:2 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.TTYPE:3 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODERD:4 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.ADDMODEWR:5 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.AUTOINIT:6 TEST.VALUE:FPGA.<>.fpgaDMAWriteControlRecord.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.channel:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.SADD:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.DADD:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.CHCTRL:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRCNT:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELCNT:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELDOFFSET:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ELSOFFSET:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRDOFFSET:8 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.FRSOFFSET:9 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.PORTASGN:0 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.RDSIZE:1 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.WRSIZE:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.TTYPE:3 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODERD:4 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.ADDMODEWR:5 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.AUTOINIT:6 TEST.EXPECTED:uut_prototype_stubs.dmaSetCtrlPacket.g_dmaCTRLPKT.COMBO:7 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.channel:2 TEST.EXPECTED:uut_prototype_stubs.dmaSetChEnable.type:0 TEST.END