###########################################################################
#
# Copyright (c) 2021-2024 Diality Inc. - All Rights Reserved.
#
# THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
# WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
#
# @file    test_voltages.py
#
# @author  (last)      Sean Nash
# @date    (last)      23-Jul-2021
# @author  (original)  Sean Nash
# @date    (original)  16-Apr-2021
#
############################################################################

import sys
sys.path.append("..")
from dialin.hd.hemodialysis_device import HD
from dialin.dg.dialysate_generator import DG
from time import sleep
from dialin.hd.voltages import HDMonitoredVoltages
from dialin.dg.voltages import DGMonitoredVoltages
from dialin.hd.constants import NO_RESET

if __name__ == "__main__":
    # create an HD object called hd
    hd = HD()
    dg = DG()

    # log in to HD and DG as tester
#    if hd.cmd_log_in_to_hd() == 0:
#        print("Failed to log into HD.")
#        exit(1)
#    if dg.cmd_log_in_to_dg() == 0:
#        print("Failed to log into DG.")
#        exit(1)
#    sleep(0.1)

#    hd.rtc.cmd_set_rtc_time_and_date(0,0,9,7,5,2021)
#    exit(1)

    # override alarms/voltages broadcast interval to 50 ms
    hd.voltages.cmd_monitored_voltages_broadcast_interval_override(50,NO_RESET)
    hd.alarms.cmd_alarm_info_broadcast_interval_override(50,NO_RESET)

    x = 0

    # create log file
    with open("/home/fw/projects/dialin/tests/v_test.log", "w") as f:
        # write column header labels to log file
        header = "HD1.2V, HD3.3V, HD5V Logic, HD5V Sensors, HD24V, HD24V Regen, HDFPGA RefV, HDPBA RefV, HDAlmCurrHg, HDAlmCurrLg, HDAlmBckpCurr," + \
                 "DG1V FPGA, DG1.2V, DG1.8V Proc, DG1.8V FPGA, DGVRef, DGRef1, DGRef2, DG3.3V, DG3.3V Sensors, DG5V Logic, DG5V Sensors, DG5V P/S Gate Drvr, DG24V, DG24V Htr, DG24V Trim\n"
        f.write(header)

        # write monitored voltages related data from HD to log file
        while True:
            x = x + 1
#            if x == 40:
#                hd.alarms.cmd_alarm_backup_audio_current_override(0.0,NO_RESET)
#            if x == 80:
#                hd.watchdog.cmd_watchdog_task_check_in_override(0,1,NO_RESET)
            vHd = hd.voltages.get_monitored_voltages()
            vDg = dg.voltages.get_monitored_voltages()
            hdVoltageData = '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_1_2V.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_3_3V.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_5V_LOGIC.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_5V_SENSORS.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_24V.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_24V_REGEN.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_FPGA_REF_V.value]) + \
                ", " + '{:11.6f}'.format(vHd[HDMonitoredVoltages.MONITORED_LINE_PBA_REF_V.value]) + \
                ", " + '{:11.6f}'.format(hd.alarms.alarm_audio_curr_hg) + \
                ", " + '{:11.6f}'.format(hd.alarms.alarm_audio_curr_lg) + \
                ", " + '{:11.6f}'.format(hd.alarms.alarm_backup_audio_curr)
            dgVoltageData = ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_1V_FPGA.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_1_2V_PROC.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_1_8V_PROC.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_1_8V_FPGA.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_V_REF.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_EXT_ADC_1_REF_V.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_EXT_ADC_2_REF_V.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_3_3V.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_3_3V_SENSORS.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_5V_LOGIC.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_5V_SENSORS.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_PS_GATE_DRIVER_V.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_24V_MAIN.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_24V_PRIM_HTR_V.value]) + \
                ", " + '{:11.6f}'.format(vDg[DGMonitoredVoltages.MONITORED_LINE_24V_TRIM_HTR_V.value])
            sleep(0.05)

            # log data
            f.write(hdVoltageData+dgVoltageData+"\n")

            # print to console
            print(hdVoltageData)
            print(dgVoltageData)