/**************************************************************************
*
* Copyright (c) 2019-2024 Diality Inc. - All Rights Reserved.
*
* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
*
* @file    FPGA.h
*
* @author  (last)      Sean Nash
* @date    (last)      05-Sep-2023
*
* @author  (original)  Dara Navaei
* @date    (original)  05-Nov-2019
*
***************************************************************************/

#ifndef __FPGA_H__
#define __FPGA_H__

#ifdef _TD_
#include "TDCommon.h"
#endif
#ifdef _DD_
#include "DDCommon.h"
#endif
#ifdef _RO_
#include "ROCommon.h"
#endif

#include "Interrupts.h"


/**
 *  @defgroup FPGA FPGA
 *  @brief FPGA service module.
 *  The FPGA module manages communication between the HD and the FPGA via UART.
 *  This module is driven by the Priority Task via calls to two FPGA executive functions:
 *     1) an incoming executive manages the states of the state machine that deal with responses and data received from the FPGA
 *     2) an outgoing executive manages transmission of write and read commands to the FPGA.
 *  This module first reads the header record that includes the FPGA ID and revision and
 *  verifies the FPGA ID to check FPGA communication.  It then initializes and configures the ADCs and
 *  various other sensors that are interfaced via the FPGA. Then, it essentially enters an infinite loop
 *  where a bulk write command updates actuator set points and a bulk read command retrieves the latest sensor readings.
 *
 *  @addtogroup FPGA
 *  @{
 */

// ********** public definitions **********

// ********** public function prototypes **********

void initFPGA( U08* hdr, U08* sen, U08* act, U32 hdrSize, U32 senSize, U32 actSize );
void execFPGAIn( void );
void execFPGAOut( void );

void signalFPGAReceiptCompleted( void );
void signalFPGATransmitCompleted( void );

/**@}*/

#endif