/* * FPGA.c * * Created on: Aug 15, 2024 * Author: fw */ #include // For memcpy and memset #include "sci.h" #include "sys_dma.h" #include "Comm.h" #include "Download.h" #include "FPGA.h" #include "Timers.h" #include "Utilities.h" #define QUEUE_MAX_SIZE 20 ///< Max queue size. #define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. #define FPGA_MAX_READ_SIZE ( FPGA_PAGE_SIZE - 1 ) #define FPGA_WRITE_CMD_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA write command buffer byte length. #define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. #define FPGA_WRITE_RSP_BUFFER_LEN 8 ///< FPGA write command response buffer byte length. #define FPGA_READ_RSP_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA read command response buffer byte length. #define SCI2_RECEIVE_DMA_REQUEST 28 ///< Serial port 2 receive DMA request line. #define SCI2_TRANSMIT_DMA_REQUEST 29 ///< Serial port 2 transmit DMA request line. #define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. #define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. #define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. #define FPGA_WRITE_CMD_CODE 0x55 ///< FPGA write command code. #define FPGA_WRITE_CMD_ACK 0xA5 ///< FPGA write command ACK code. #define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. #define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. #define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. #define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. #define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO does this vary? #define FPGA_FLASH_CONTROL_REG_ADDR 0x090E #define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe #define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe #define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe #define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. #define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) #define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. #define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. #define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) // TODO Get this value from Noe, make sure the index is the same in all of the stacks #define FPGA_FLASH_STATUS_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) #define FPGA_FIFO_COUNT_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) #define UPDATE_REQUESTED_VALUE 1 #define FPGA_FIFO_SIZE_BYTES 1024 #define FPGA_FIFO_COUNT_MASK 0x03FF #define FPGA_ERASE_FIFO_CMD_OK ( 1 << 11 ) #define FPGA_FLASH_STATUS_OK ( 1 << 15 ) typedef enum { FPGA_COMM_IDLE = 0, FPGA_COMM_READ_IN_PROGRESS, FPGA_COMM_READ_RESP_RECEIVED, FPGA_COMM_WRITE_IN_PROGRESS, FPGA_COMM_WRITE_RESP_RECEIVED, NUM_OF_FPGA_COMM_STATUS } FPGA_COMM_STATE_T; typedef enum { FPGA_READ_HEADER = 0, FPGA_READ_UPDATE_REG, FPGA_WRITE_UPDATE_REG, FPGA_RESET_FLASH, FPGA_ERASE_FIFO, FPGA_ENABLE_FLASH, FPGA_READ_MULTI_BOOT_STATUS, FPGA_FLASH_WRITE_DATA, FPGA_SELF_CONFIGURE, NUM_OF_FPGA_JOBS, } FPGA_JOBS_T; typedef enum { FPGA_IDLE_STATE = 0, FPGA_WRITE_TO_FPGA_STATE, FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE, FPGA_READ_FROM_FPGA_STATE, FPGA_RCV_READ_RESP_FROM_FPGA_STATE, NUM_OF_FPGA_STATES } FPGA_STATE_T; #pragma pack(push,1) typedef struct { U16 fpgaJobAddress; U16 fpgaJobSize; U08* fpgaWriteStartAddress; U08 fpgaIsJobWrite; } FPGA_JOB_SPECS_T; typedef struct { U08 fpgaJobsQueue[ QUEUE_MAX_SIZE ]; U08 fpgaJobRearIndex; U08 fpgaJobFrontIndex; U08 fpgaJobsQueueCount; U08 fpgaCurrentJob; FPGA_COMM_STATE_T fpgaCommRead; FPGA_COMM_STATE_T fpgaCommWrite; } FPGA_JOBS_Q_STATUS_T; typedef struct { BOOL hasUpdateRegsBeenRqstd; U16 fifoRemainingCount; FPGA_FLASH_STATE_T fpgaFlashState; U32 startTime; } FPGA_FLASH_STATUS_T; /// Record structure for FPGA header read. typedef struct { U08 fpgaId; ///< Reg 0. FPGA ID code. Checked against expected value at power up to verify basic FPGA communication and operation. U08 fpgaRev; ///< Reg 1. FPGA revision (minor) being reported. U08 fpgaRevMajor; ///< Reg 2. FPGA revision (major) being reported. U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported. U16 fpgaStatus; ///< Reg 4. FPGA status register. } FPGA_HEADER_T; // Read only on FPGA #pragma pack(pop) // FPGA comm buffers static U08 fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_BUFFER_LEN ]; ///< FPGA write command buffer. Holds the next FPGA write command to be transmitted. static U08 fpgaReadCmdBuffer[ FPGA_READ_CMD_BUFFER_LEN ]; ///< FPGA read command buffer. Holds the next FPGA read command to be transmitted. static U08 fpgaWriteResponseBuffer[ FPGA_WRITE_RSP_BUFFER_LEN ]; ///< FPGA write command response buffer. Memory reserved to capture the response to the last FPGA write command. static U08 fpgaReadResponseBuffer[ FPGA_READ_RSP_BUFFER_LEN ]; ///< FPGA read command response buffer. Memory reserved to capture the response to the last FPGA read command. // DMA control records static g_dmaCTRL fpgaDMAWriteControlRecord; ///< DMA record for controlling a DMA write command transmission from buffer. static g_dmaCTRL fpgaDMAWriteRespControlRecord; ///< DMA record for controlling a DMA write command reception to buffer. static g_dmaCTRL fpgaDMAReadControlRecord; ///< DMA record for controlling a DMA read command transmission from buffer. static g_dmaCTRL fpgaDMAReadRespControlRecord; ///< DMA record for controlling a DMA read command reception to buffer. static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data. static FPGA_STATE_T fpgaState; static U08 fpgaUpdateRegisterStatus; static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; static FPGA_FLASH_STATUS_T fpgaFlashStatus; static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; static U32 fpgaDataLenToWrite; static U32 TESTREMOVE = 0; // TODO remove static U32 countRemove = 0; // TODO remove static U32 nonzeroCounter = 0; // TODO remove static U16 nonZeroCount[10000]; // TODO remove static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF }; // TODO update with the real FPGA IDs static const U16 DISABLE_UPDATE_REG_CMD = 5; // TODO what is this value? 0? static const U08 FPGA_RESET_FLASH_CMD = 0x01; static const U08 FPGA_ERASE_FIFO_CMD = 0x08; static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; static const U08 FPGA_SELF_CONFIG_CMD = 0x03; static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // FPGA_READ_UPDATE_REG { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), (U08*)&DISABLE_UPDATE_REG_CMD, TRUE }, // FPGA_WRITE_UPDATE_REG { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( U32 ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; static void initDMA( void ); static void consumeUnexpectedData( void ); static void requestFlashRegistersStatus( void ); static void processFPGAFlashRegistersRead( void ); static void setupDMAForReadResp( U32 bytes2Receive ); static void setupDMAForReadCmd( U32 bytes2Transmit ); static void startDMAReceiptOfReadResp( void ); static void startDMAReadCmd( void ); static void setupDMAForWriteCmd( U32 bytes2Transmit ); static void startDMAWriteCmd( void ); static void setupDMAForWriteResp( U32 bytes2Receive ); static void startDMAReceiptOfWriteResp( void ); static void resetFPGACommFlags( void ); static void enqueue( FPGA_JOBS_T job ); static void dequeue( void ); static U08 peekFromQueue( void ); static BOOL isQueueFull( void ); static FPGA_STATE_T handleFPGAIdleState( void ); static FPGA_STATE_T handleFPGAWriteToFPGAState( void ); static FPGA_STATE_T handleFPGAReceiveWriteRespFromFPGAState( void ); static FPGA_STATE_T handleFPGAReadFromFPGAState( void ); static FPGA_STATE_T handleFPGAReceiveReadRespFromFPGAState( void ); void initFPGA( void ) { memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); memset( &fpgaJobsQStatus, 0x0, sizeof( FPGA_JOBS_Q_STATUS_T ) ); memset( &fpgaFlashStatus, 0x0, sizeof( FPGA_FLASH_STATUS_T ) ); initDMA(); consumeUnexpectedData(); enqueue( FPGA_READ_HEADER ); enqueue( FPGA_READ_UPDATE_REG ); enqueue( FPGA_READ_MULTI_BOOT_STATUS ); fpgaState = FPGA_IDLE_STATE; fpgaUpdateRegisterStatus = 0; } void execFPGA( void ) { switch( fpgaState ) { case FPGA_IDLE_STATE: fpgaState = handleFPGAIdleState(); break; case FPGA_WRITE_TO_FPGA_STATE: fpgaState = handleFPGAWriteToFPGAState(); break; case FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE: fpgaState = handleFPGAReceiveWriteRespFromFPGAState(); break; case FPGA_READ_FROM_FPGA_STATE: fpgaState = handleFPGAReadFromFPGAState(); break; case FPGA_RCV_READ_RESP_FROM_FPGA_STATE: fpgaState = handleFPGAReceiveReadRespFromFPGAState(); break; default: // Do nothing break; } } void signalFPGAReceiptCompleted( void ) { if ( FPGA_COMM_WRITE_IN_PROGRESS == fpgaJobsQStatus.fpgaCommWrite ) { fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_WRITE_RESP_RECEIVED; requestFlashRegistersStatus(); } else if ( FPGA_COMM_READ_IN_PROGRESS == fpgaJobsQStatus.fpgaCommRead ) { fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_RESP_RECEIVED; if ( TRUE == fpgaFlashStatus.hasUpdateRegsBeenRqstd ) { processFPGAFlashRegistersRead(); } } } BOOL hasUpdateBeenRequested( void ) { BOOL status = FALSE; if ( ( FPGA_IDLE_STATE == fpgaState ) && ( UPDATE_REQUESTED_VALUE == fpgaUpdateRegisterStatus ) ) { status = TRUE; fpgaUpdateRegisterStatus = 0; enqueue( FPGA_WRITE_UPDATE_REG ); } return status; } BOOL isFPGAIDValid( void ) { BOOL status = ( STACK_FPGA_ID[ BL_STACK_ID ] == fpgaHeader.fpgaId ? TRUE : FALSE ); return status; } FPGA_FLASH_STATE_T getFPGAFlashState( void ) { return fpgaFlashStatus.fpgaFlashState; } void signalFPGAToPrepareForUpdate( void ) { if ( FALSE == isQueueFull() ) { enqueue( FPGA_RESET_FLASH ); enqueue( FPGA_ERASE_FIFO ); enqueue( FPGA_ENABLE_FLASH ); } } void signalFPGAToWriteToFlash( U08* data, U32 len ) { if ( FALSE == isQueueFull() ) { memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); enqueue( FPGA_FLASH_WRITE_DATA ); fpgaDataLenToWrite = len; memcpy( fpgaDataToWriteBuffer, data, len ); fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_BUSY; } } void signalFPGAToSelfConfigure( void ) { if ( FALSE == isQueueFull() ) { enqueue( FPGA_SELF_CONFIGURE ); } } // ********** private functions ********** static void initDMA( void ) { // Enable interrupt notifications for FPGA serial port sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); // Assign DMA channels to h/w DMA requests dmaReqAssign( DMA_CH0, SCI2_RECEIVE_DMA_REQUEST ); dmaReqAssign( DMA_CH2, SCI2_TRANSMIT_DMA_REQUEST ); // Set DMA channel priorities dmaSetPriority( DMA_CH0, HIGHPRIORITY ); dmaSetPriority( DMA_CH2, LOWPRIORITY ); // Enable DMA block transfer complete interrupts dmaEnableInterrupt( DMA_CH0, BTC ); dmaEnableInterrupt( DMA_CH2, BTC ); // Initialize FPGA DMA Write Control Record fpgaDMAWriteControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteCmdBuffer; // Transfer source address fpgaDMAWriteControlRecord.DADD = (U32)(&(scilinREG->TD)); // Dest. is SCI2 xmit register fpgaDMAWriteControlRecord.CHCTRL = 0; // No chaining fpgaDMAWriteControlRecord.ELCNT = 1; // Frame is 1 element fpgaDMAWriteControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1; // Source addressing mode is post-increment fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // Dest. addressing mode is fixed fpgaDMAWriteControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off fpgaDMAWriteControlRecord.ELSOFFSET = 0; // Not used fpgaDMAWriteControlRecord.ELDOFFSET = 0; // Not used fpgaDMAWriteControlRecord.FRSOFFSET = 0; // Not used fpgaDMAWriteControlRecord.FRDOFFSET = 0; // Not used // Initialize FPGA DMA Write Response Control Record fpgaDMAWriteRespControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) fpgaDMAWriteRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // Source is SCI2 recv register fpgaDMAWriteRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // Transfer destination address fpgaDMAWriteRespControlRecord.CHCTRL = 0; // No chaining fpgaDMAWriteRespControlRecord.ELCNT = 1; // Frame is 1 element fpgaDMAWriteRespControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known fpgaDMAWriteRespControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAWriteRespControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAWriteRespControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer fpgaDMAWriteRespControlRecord.ADDMODERD = ADDR_FIXED; // Source addressing mode is fixed fpgaDMAWriteRespControlRecord.ADDMODEWR = ADDR_INC1; // Dest. addressing mode is post-increment fpgaDMAWriteRespControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // Not used fpgaDMAWriteRespControlRecord.ELSOFFSET = 0; // Not used fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // Not used fpgaDMAWriteRespControlRecord.FRSOFFSET = 0; // Not used // Initialize FPGA DMA Read Control Record fpgaDMAReadControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) fpgaDMAReadControlRecord.SADD = (U32)fpgaReadCmdBuffer; // Transfer source address fpgaDMAReadControlRecord.DADD = (U32)(&(scilinREG->TD)); // Dest. is SCI2 xmit register fpgaDMAReadControlRecord.CHCTRL = 0; // No chaining fpgaDMAReadControlRecord.ELCNT = 1; // Frame is 1 element fpgaDMAReadControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known fpgaDMAReadControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAReadControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAReadControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer fpgaDMAReadControlRecord.ADDMODERD = ADDR_INC1; // Source addressing mode is post-increment fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // Dest. addressing mode is fixed fpgaDMAReadControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off fpgaDMAReadControlRecord.ELSOFFSET = 0; // Not used fpgaDMAReadControlRecord.ELDOFFSET = 0; // Not used fpgaDMAReadControlRecord.FRSOFFSET = 0; // Not used fpgaDMAReadControlRecord.FRDOFFSET = 0; // Not used // Initialize FPGA DMA Read Response Control Record fpgaDMAReadRespControlRecord.PORTASGN = 4; // Port B (only choice per datasheet) fpgaDMAReadRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // Source is SCI2 recv register fpgaDMAReadRespControlRecord.DADD = (U32)fpgaReadResponseBuffer; // Transfer destination address fpgaDMAReadRespControlRecord.CHCTRL = 0; // No chaining fpgaDMAReadRespControlRecord.ELCNT = 1; // Frame is 1 element fpgaDMAReadRespControlRecord.FRCNT = 0; // Block is TBD frames - will be populated later when known fpgaDMAReadRespControlRecord.RDSIZE = ACCESS_8_BIT; // Element size is 1 byte fpgaDMAReadRespControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAReadRespControlRecord.TTYPE = FRAME_TRANSFER; // Transfer type is block transfer fpgaDMAReadRespControlRecord.ADDMODERD = ADDR_FIXED; // Source addressing mode is fixed fpgaDMAReadRespControlRecord.ADDMODEWR = ADDR_INC1; // Dest. addressing mode is post-increment fpgaDMAReadRespControlRecord.AUTOINIT = AUTOINIT_OFF; // Auto-init off fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // Not used fpgaDMAReadRespControlRecord.ELSOFFSET = 0; // Not used fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // Not used fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // Not used } static void consumeUnexpectedData( void ) { // Clear any errors sciRxError( scilinREG ); // If a byte is pending read, read it if ( sciIsRxReady( scilinREG ) != 0 ) { sciReceiveByte( scilinREG ); } } static void requestFlashRegistersStatus( void ) { U16 jobAddress = JOBS_SPECS[ FPGA_READ_MULTI_BOOT_STATUS ].fpgaJobAddress; U08 jobSize = JOBS_SPECS[ FPGA_READ_MULTI_BOOT_STATUS ].fpgaJobSize; U16 crc = 0; // Construct read command to read 3 registers starting at address 0 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 3 ] = jobSize; crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); // Prep DMA for sending the read cmd and receiving the response fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS; fpgaFlashStatus.hasUpdateRegsBeenRqstd = TRUE; setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) ); startDMAReceiptOfReadResp(); startDMAReadCmd(); } static void processFPGAFlashRegistersRead( void ) { if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) { U32 rspSize = FPGA_READ_RSP_HDR_LEN + JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { U16 flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); U16 fifoStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) ], fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) - 1 ] ); fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_NOT_READY; fpgaFlashStatus.fifoRemainingCount = FPGA_FIFO_SIZE_BYTES - ( FPGA_FIFO_COUNT_MASK & fifoStatus ); fpgaFlashStatus.hasUpdateRegsBeenRqstd = FALSE; if ( ( flashStatus & FPGA_ERASE_FIFO_CMD_OK ) == FPGA_ERASE_FIFO_CMD_OK ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; } if ( ( flashStatus & FPGA_FLASH_STATUS_OK ) == FPGA_FLASH_STATUS_OK ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; } if ( fpgaFlashStatus.fifoRemainingCount >= SW_UPDATE_FLASH_BUFFER_SIZE ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; } else { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_FIFO_FULL; } nonZeroCount[nonzeroCounter] = fpgaFlashStatus.fifoRemainingCount; nonzeroCounter = INC_WRAP( nonzeroCounter, 0, 10000 - 1 ); // TODO remove if ( fpgaFlashStatus.fifoRemainingCount < FPGA_FIFO_SIZE_BYTES ) { BOOL dara = FALSE; } // TODO remove } } } static void setupDMAForReadResp( U32 bytes2Receive ) { // Verify # of bytes does not exceed buffer length if ( bytes2Receive <= FPGA_READ_RSP_BUFFER_LEN ) { fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; } } static void setupDMAForReadCmd( U32 bytes2Transmit ) { // Verify # of bytes does not exceed buffer length if ( bytes2Transmit <= FPGA_READ_CMD_BUFFER_LEN ) { fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; } } static void startDMAReceiptOfReadResp( void ) { dmaSetCtrlPacket( DMA_CH0, fpgaDMAReadRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); setSCI2DMAReceiveInterrupt(); } static void startDMAReadCmd( void ) { dmaSetCtrlPacket( DMA_CH2, fpgaDMAReadControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); setSCI2DMATransmitInterrupt(); } /*********************************************************************//** * @brief * The setupDMAForWriteCmd function sets the byte count for the next DMA * write command to the FPGA. * @details Inputs: none * @details Outputs: number of bytes for next FPGA write command is set * @param bytes2Transmit number of bytes to be transmitted via DMA to the FPGA * @return none *************************************************************************/ static void setupDMAForWriteCmd( U32 bytes2Transmit ) { // Verify # of bytes does not exceed buffer length if ( bytes2Transmit <= FPGA_WRITE_CMD_BUFFER_LEN ) { fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; } } /*********************************************************************//** * @brief * The startDMAWriteCmd function initiates the DMA transmit for the next * DMA write command to the FPGA. * @details Inputs: none * @details Outputs: DMA write command to FPGA is initiated * @return none *************************************************************************/ static void startDMAWriteCmd( void ) { dmaSetCtrlPacket( DMA_CH2, fpgaDMAWriteControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); setSCI2DMATransmitInterrupt(); } /*********************************************************************//** * @brief * The setupDMAForWriteResp function sets the expected byte count for the * next DMA write command response from the FPGA. * @details Inputs: none * @details Outputs: number of expected bytes for next FPGA write command response is set * @param bytes2Receive number of bytes expected to be transmitted via DMA from the FPGA * @return none *************************************************************************/ static void setupDMAForWriteResp( U32 bytes2Receive ) { // Verify # of bytes does not exceed buffer length if ( bytes2Receive <= FPGA_WRITE_RSP_BUFFER_LEN ) { fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; } } /*********************************************************************//** * @brief * The startDMAReceiptOfWriteResp function initiates readiness of the DMA * receiver for the next DMA write command response from the FPGA. * @details Inputs: none * @details Outputs: DMA write command response is ready to be received from the FPGA * @return none *************************************************************************/ static void startDMAReceiptOfWriteResp( void ) { dmaSetCtrlPacket( DMA_CH0, fpgaDMAWriteRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); setSCI2DMAReceiveInterrupt(); } static void resetFPGACommFlags( void ) { fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_IDLE; fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_IDLE; } static void enqueue( FPGA_JOBS_T job ) { U08 currentRearIndex = fpgaJobsQStatus.fpgaJobRearIndex; fpgaJobsQStatus.fpgaJobsQueue[ currentRearIndex ] = job; fpgaJobsQStatus.fpgaJobsQueueCount++; fpgaJobsQStatus.fpgaJobRearIndex = INC_WRAP( currentRearIndex, 0, QUEUE_MAX_SIZE - 1 ); } static void dequeue( void ) { U08 tempIndex; _disable_IRQ(); tempIndex = fpgaJobsQStatus.fpgaJobFrontIndex; if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 ) { U08 frontIndex = fpgaJobsQStatus.fpgaJobFrontIndex; fpgaJobsQStatus.fpgaJobFrontIndex = INC_WRAP( frontIndex, 0, QUEUE_MAX_SIZE - 1 ); fpgaJobsQStatus.fpgaCurrentJob = fpgaJobsQStatus.fpgaJobsQueue[ tempIndex ]; } if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 ) { fpgaJobsQStatus.fpgaJobsQueueCount--; } _enable_IRQ(); } static U08 peekFromQueue( void ) { _disable_IRQ(); U08 frontIndex = fpgaJobsQStatus.fpgaJobFrontIndex; U08 frontIndexUpdate = INC_WRAP( frontIndex, 0, QUEUE_MAX_SIZE - 1 ); _enable_IRQ(); return frontIndexUpdate; } static BOOL isQueueFull( void ) { BOOL isFull = FALSE; if ( fpgaJobsQStatus.fpgaJobsQueueCount >= ( QUEUE_MAX_SIZE - 1 ) ) { isFull = TRUE; } return isFull; } static FPGA_STATE_T handleFPGAIdleState( void ) { FPGA_STATE_T state = FPGA_IDLE_STATE; requestFlashRegistersStatus(); if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 ) { BOOL isDequeueAllowed = TRUE; if ( ( FPGA_FLASH_WRITE_DATA == peekFromQueue() ) && ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) ) { isDequeueAllowed = FALSE; } if ( TRUE == isDequeueAllowed ) { dequeue(); state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); } } // TODo remove if ( ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) && ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) ) { nonZeroCount[ nonzeroCounter ] = fpgaFlashStatus.fifoRemainingCount; nonzeroCounter++; } if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob ) { BOOL test = FALSE; } // TODo remove return state; } static FPGA_STATE_T handleFPGAWriteToFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; U16 crc = 0; U16 jobAddress = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobAddress; U16 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; if ( ( fpgaDataLenToWrite != SW_UPDATE_FLASH_BUFFER_SIZE ) && ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) ) { jobSize = (U16)fpgaDataLenToWrite; } // TODO remove if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) { BOOL Test = FALSE; } // TODO remove U08* value2Write = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaWriteStartAddress; U16 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; U16 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; memcpy( &fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ], value2Write, jobSize ); // Construct bulk read command to read sensor data registers starting at address 8 fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + jobSize ); fpgaWriteCmdBuffer[ firstCRCIndex ] = GET_MSB_OF_WORD( crc ); fpgaWriteCmdBuffer[ secondCRCIndex ] = GET_LSB_OF_WORD( crc ); // Prep DMA for sending the read cmd and receiving the response fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_WRITE_IN_PROGRESS; // Prep DMA for sending the bulk write cmd and receiving its response setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + jobSize + FPGA_CRC_LEN ); setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN + FPGA_CRC_LEN ); // Initiate bulk write command and its receipt - read will follow startDMAReceiptOfWriteResp(); startDMAWriteCmd(); return state; } static FPGA_STATE_T handleFPGAReceiveWriteRespFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; if ( FPGA_COMM_WRITE_RESP_RECEIVED == fpgaJobsQStatus.fpgaCommWrite ) { if ( FPGA_WRITE_CMD_ACK == fpgaWriteResponseBuffer[ 0 ] ) { // Message is an ack - check CRC U32 rspSize = FPGA_READ_RSP_HDR_LEN; U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaWriteResponseBuffer[ crcPos ], fpgaWriteResponseBuffer[ crcPos + 1 ] ); // Does the FPGA response CRC checkout? if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) ) { if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; sendFPGAAckNackStatus( ACK ); TESTREMOVE += fpgaDataLenToWrite;// TODO REMOVE countRemove += 1;// TODO REMOVE } // CRC passed state = FPGA_IDLE_STATE; } else { // TODO error handling } } memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } requestFlashRegistersStatus(); return state; } static FPGA_STATE_T handleFPGAReadFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_READ_RESP_FROM_FPGA_STATE; U16 crc = 0; U16 jobAddress = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobAddress; U08 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; // Construct read command to read 3 registers starting at address 0 fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 3 ] = jobSize; crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); // Prep DMA for sending the read cmd and receiving the response fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS; fpgaFlashStatus.startTime = getMSTimerCount(); setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) ); startDMAReceiptOfReadResp(); startDMAReadCmd(); return state; } static FPGA_STATE_T handleFPGAReceiveReadRespFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_READ_RESP_FROM_FPGA_STATE; if ( FPGA_COMM_READ_RESP_RECEIVED == fpgaJobsQStatus.fpgaCommRead ) { if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) { U32 rspSize = FPGA_READ_RSP_HDR_LEN + JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); // Does the FPGA response CRC check out? if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) { switch( fpgaJobsQStatus.fpgaCurrentJob ) { case FPGA_READ_HEADER: memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); break; case FPGA_READ_UPDATE_REG: fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; break; default: // Do nothing break; } memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); state = FPGA_IDLE_STATE; } } } if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) ) { state = FPGA_IDLE_STATE; } resetFPGACommFlags(); // Should not be any data received at this time consumeUnexpectedData(); return state; }