Contents

Testcase Management Report

Configuration Data

Environment NameCOMM
Date of Report Creation05 DEC 2019
Time of Report Creation2:42:01 PM

Overall Results

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Testcases 23 / 23 PASS
Expecteds 23 / 23 PASS
Statement Coverage 20 / 20 (100%)
Branch Coverage 53 / 53 (100%)
Pairs Coverage 12 / 12 (100%)

Testcase Management

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UnitSubprogramTest CasesExecution Date and TimePass/Fail
CommsignalCANXmitsInitiatedsignalCANXmitsInitiated_NominalPath05 DEC 2019 2:37:14 PMPASS 1 / 1
 signalCANXmitsCompletedsignalCANXmitsCompleted_NominalPath05 DEC 2019 2:37:42 PMPASS 1 / 1
 signalSCI1XmitsInitiatedsignalSCI1XmitsInitiated_NominalPath05 DEC 2019 2:37:58 PMPASS 1 / 1
 signalSCI1XmitsCompletedsignalSCI1XmitsCompleted_NominalPath05 DEC 2019 2:38:23 PMPASS 1 / 1
 setSCI1DMAReceiveInterruptsetSCI1DMAReceiveInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 setSCI1DMATransmitInterruptsetSCI1DMATransmitInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 clearSCI1DMAReceiveInterruptclearSCI1DMAReceiveInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 clearSCI1DMATransmitInterruptclearSCI1DMATransmitInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 setSCI2DMAReceiveInterruptsetSCI2DMAReceiveInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 setSCI2DMATransmitInterruptsetSCI2DMATransmitInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 clearSCI2DMAReceiveInterruptclearSCI2DMAReceiveInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 clearSCI2DMATransmitInterruptclearSCI2DMATransmitInterrupt05 DEC 2019 2:33:46 PMPASS 1 / 1
 isSCI1DMATransmitInProgressisSCI1DMATransmitInProgress_DMABusy05 DEC 2019 2:33:46 PMPASS 1 / 1
  isSCI1DMATransmitInProgress_NotBusy05 DEC 2019 2:33:46 PMPASS 1 / 1
  isSCI1DMATransmitInProgress_TransmitterBusy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isSCI1DMATransmitInProgress_InProgress05 DEC 2019 2:40:50 PMPASS 1 / 1
 isSCI2DMATransmitInProgressisSCI2DMATransmitInProgress_DMABusy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isSCI2DMATransmitInProgress_NotBusy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isSCI2DMATransmitInProgress_TransmitterBusy05 DEC 2019 2:33:47 PMPASS 1 / 1
 isCAN1TransmitInProgressisCAN1TransmitInProgress_Ch1_8_Busy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isCAN1TransmitInProgress_Ch9_16_Busy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isCAN1TransmitInProgress_NotBusy05 DEC 2019 2:33:47 PMPASS 1 / 1
  isCAN1TransmitInProgress_InProgress05 DEC 2019 2:41:51 PMPASS 1 / 1
TOTALS1523 PASS 23 / 23

Metrics

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Statement+MC/DC

UnitSubprogramComplexityStatementsBranchesPairs
CommsignalCANXmitsInitiated11 / 1 (100%)1 / 1 (100%)
 signalCANXmitsCompleted11 / 1 (100%)1 / 1 (100%)
 signalSCI1XmitsInitiated11 / 1 (100%)1 / 1 (100%)
 signalSCI1XmitsCompleted11 / 1 (100%)1 / 1 (100%)
 setSCI1DMAReceiveInterrupt11 / 1 (100%)1 / 1 (100%)
 setSCI1DMATransmitInterrupt11 / 1 (100%)1 / 1 (100%)
 clearSCI1DMAReceiveInterrupt11 / 1 (100%)1 / 1 (100%)
 clearSCI1DMATransmitInterrupt11 / 1 (100%)1 / 1 (100%)
 setSCI2DMAReceiveInterrupt11 / 1 (100%)1 / 1 (100%)
 setSCI2DMATransmitInterrupt11 / 1 (100%)1 / 1 (100%)
 clearSCI2DMAReceiveInterrupt11 / 1 (100%)1 / 1 (100%)
 clearSCI2DMATransmitInterrupt11 / 1 (100%)1 / 1 (100%)
 isSCI1DMATransmitInProgress43 / 3 (100%)17 / 17 (100%)5 / 5 (100%)
 isSCI2DMATransmitInProgress43 / 3 (100%)15 / 15 (100%)4 / 4 (100%)
 isCAN1TransmitInProgress22 / 2 (100%)9 / 9 (100%)3 / 3 (100%)
TOTALS152220 / 20 (100%)53 / 53 (100%)12 / 12 (100%)
GRAND TOTALS152220 / 20 (100%)53 / 53 (100%)12 / 12 (100%)