/* * Copyright (C) 2021-2025, Digi International Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /dts-v1/; /* * The device tree for the ConnectCore 8M Mini DVK is made out of different * device tree include files that contain the common hardware of all variants. * * A U-Boot boot script applies additional overlays for variant-specific * hardware, including: * - Overlay for ConnectCore 8M Mini variants with Wi-Fi * - Overlay for ConnectCore 8M Mini variants with Bluetooth * * If you are not going to use Digi's boot script, you can: * - Manually add the overlays to U-Boot's "overlays" environment variable * - Apply the overlay fragments manually to this device tree, if you don't * use Digi U-Boot's "dboot" command */ /* i.MX8MM CPU */ #include "../freescale/imx8mm.dtsi" /* Digi ConnectCore 8M Mini */ #include "ccimx8mm.dtsi" #include / { model = "Digi International ConnectCore 8M Mini DVK."; compatible = "digi,ccimx8mm-dvk", "digi,ccimx8mm", "digi,ccimx8m", "digi,ccimx8", "fsl,imx8mm"; digi,machine,name = "ccimx8mm-dvk"; chosen { bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; stdout-path = &uart1; }; lvds_backlight: lvds_backlight { compatible = "pwm-backlight"; pwms = <&mca_pwm0 4 100000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <80>; power-supply = <®_5v_board>; status = "okay"; }; /* fixed crystal dedicated to mcp2517fd */ mcp2517fd_osc: mcp2517fd_osc { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <40000000>; }; pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_3v3_ext: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "3v3_ext"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&mca_gpio 9 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-boot-on; }; reg_1v8_ext: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "1v8_ext"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&mca_gpio 14 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-boot-on; }; reg_3v3_eth0: regulator@3 { compatible = "regulator-fixed"; reg = <3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3_eth0>; regulator-name = "3v3_eth0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <10000>; vin-supply = <®_3v3_ext>; }; reg_5v_board: regulator@4 { compatible = "regulator-fixed"; reg = <4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_5v_board>; regulator-name = "5v_board"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_3v3_audio: regulator@5 { compatible = "regulator-fixed"; reg = <5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3_aud>; regulator-name = "3v3_audio"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; enable-active-high; startup-delay-us = <1000>; vin-supply = <®_3v3_ext>; }; reg_3v3_usb_hub: regulator@6 { compatible = "regulator-fixed"; reg = <6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3_usb_hub>; regulator-name = "3v3_usb_hub"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <®_3v3_ext>; }; reg_3v3_board: regulator@7 { compatible = "regulator-fixed"; reg = <7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_3v3_board>; regulator-name = "3v3_board"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; }; }; lvds_panel: lvds_panel { compatible = "panel-lvds"; status = "okay"; backlight = <&lvds_backlight>; power-supply = <®_5v_board>; data-mapping = "vesa-24"; dual-channel; width-mm = <364>; height-mm = <216>; panel-timing { clock-frequency = <136687500>; hactive = <1920>; hfront-porch = <33>; hback-porch = <50>; hsync-len = <22>; vactive = <1080>; vfront-porch = <4>; vback-porch = <36>; vsync-len = <5>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dual-lvds-even-pixels; panel_in_brg_even: endpoint { remote-endpoint = <&brg_out_panel_a>; }; }; port@1 { reg = <1>; dual-lvds-odd-pixels; panel_in_brg_odd: endpoint { remote-endpoint = <&brg_out_panel_b>; }; }; }; }; sound_max98089: sound-max98089 { compatible = "fsl,imx-audio-max98088"; model = "max98088-audio"; audio-cpu = <&sai2>; audio-codec = <&max98089>; audio-routing = "Headphone Jack", "HPL", "Headphone Jack", "HPR", "Ext Spk", "SPKL", "Ext Spk", "SPKR", "Line Out Jack", "RECL", "Line Out Jack", "RECR", "Mic Jack", "MIC1", "Mic Jack", "MIC2", "Line In Jack", "INA1", "Line In Jack", "INA2", "Line In Jack", "INB1", "Line In Jack", "INB2"; status = "okay"; }; hdmi-connector { compatible = "hdmi-connector"; label = "hdmi"; type = "a"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_hpd>; hdmi-pwr-supply = <®_5v_board>; hpd-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; status = "disabled"; port { hdmi_connector_in: endpoint { remote-endpoint = <<8912_out>; }; }; }; }; &csi1_bridge { fsl,mipi-mode; status = "okay"; port { csi_ep: endpoint { remote-endpoint = <&csi_mipi_ep>; }; }; }; &ecspi3 { #address-cells = <1>; #size-cells = <0>; num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; mcp2517fd: mcp2517fd@0 { reg = <0>; compatible = "microchip,mcp2517fd"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mcp2517fd>; spi-max-frequency = <20000000>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; clocks = <&mcp2517fd_osc>; xceiver-supply = <®_5v_board>; }; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1_gpio>, <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; digi,mdio-lt-supply = <®_1v8_ext>; phy-supply = <®_3v3_eth0>; phy-reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; phy-reset-duration = <1>; digi,phy-reset-in-suspend; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; at803x,eee-disabled; vddio-supply = <&vddio0>; vddio0: vddio-regulator { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; }; }; }; /* * FlexSPI port distributed among various interfaces. * Conflicts with: * - MIPI to HDMI bridge * - MIPI to LVDS bridge */ &flexspi { status = "disabled"; }; &gpu { /* * Use a table to set a fixed amount of contiguous memory used by the GPU * per memory configuration. This way we leave plenty of room for the * other system features when the memory is limited. The table's rows must * be in increasing RAM order. The GPU CMA should always be smaller than the * total CMA (see the table in the "reserved-memory" node to see the total CMA * values per memory configuration). */ digi,contiguous-size-table = < /* RAM CMA*/ 0x0 0x40000000 0x0 0x08000000 /* 1 GB variants -> 128 MB of GPU CMA */ 0x0 0x80000000 0x0 0x10000000 /* 2 GB variants -> 256 MB of GPU CMA */ 0x1 0x00000000 0x0 0x20000000 /* 4 GB variants -> 512 MB of GPU CMA */ >; status = "okay"; }; /* * I2C2 connected to Audio codec. * Also available on: * - LVDS connector * - PCIe connector * - MIPI Camera connector * - Expansion connector */ &i2c2 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* * An inconsistent reset sequence makes * the Goodix display's touch controller respond on one of two I2C * addresses: 0x14 and 0x5D. To make sure the touchscreen * works every time, the touch controller's description must * be duplicated for both addresses. */ goodix_touch: gt9271@14 { compatible = "goodix,gt9271"; reg = <0x14>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; /* LVDS interrupt */ interrupt-parent = <&gpio4>; interrupts = <28 IRQ_TYPE_EDGE_FALLING>; irq-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; reload-fw-on-resume; skip-firmware-request; vin-supply = <®_5v_board>; status = "disabled"; }; goodix_touch2: gt9271@5d { compatible = "goodix,gt9271"; reg = <0x5d>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; /* LVDS interrupt */ interrupt-parent = <&gpio4>; interrupts = <28 IRQ_TYPE_EDGE_FALLING>; irq-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; reload-fw-on-resume; skip-firmware-request; vin-supply = <®_5v_board>; status = "disabled"; }; /* Touch on Fusion 10" display */ fusion_touch: fusion@14 { compatible = "touchrev,fusion-touch"; reg = <0x14>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch>; /* LVDS interrupt */ interrupt-parent = <&gpio4>; interrupts = <28 IRQ_TYPE_EDGE_FALLING>; status = "disabled"; }; /* MIPI-CSI camera */ ov5640_mipi: ov5640_mipi@3c { compatible = "ovti,ov5640_mipi"; reg = <0x3c>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mipi>; clocks = <&clk IMX8MM_CLK_CLKO1>; clock-names = "csi_mclk"; assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; assigned-clock-parents = <&clk IMX8MM_CLK_24M>; assigned-clock-rates = <24000000>; csi_id = <0>; rst-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; mclk = <24000000>; mclk_source = <0>; port { ov5640_mipi_ep: endpoint { remote-endpoint = <&mipi_csi0_ep>; }; }; }; }; /* * I2C3 connected to LT8912 MIPI-to-HDMI bridge and SN65DSI83 MIPI-to-LVDS bridge. * Also available on the HDMI connector. */ &i2c3 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_gpio>; scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; dsi_lvds_bridge: sn65dsi84@2c { compatible = "ti,sn65dsi84"; enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lvds>; reg = <0x2c>; vcc-supply = <®_1v8_ext>; /* MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_NO_EOT_PACKET */ digi,mipi-mode-flags = <0x203>; status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; bridge_in_dsi: endpoint { remote-endpoint = <&mipi_dsi_out>; data-lanes = <1 2 3 4>; }; }; port@2 { reg = <2>; brg_out_panel_a: endpoint { remote-endpoint = <&panel_in_brg_even>; }; }; port@3 { reg = <3>; brg_out_panel_b: endpoint { remote-endpoint = <&panel_in_brg_odd>; }; }; }; }; lt_bridge: lt8912@48 { compatible = "lontium,lt8912b"; reg = <0x48>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lt8912>; reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; vdd-supply = <®_3v3_ext>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; lt8912_1_in: endpoint { data-lanes = <1 2 3 4>; remote-endpoint = <&mipi_dsi_hdmi_out>; }; }; port@1 { reg = <1>; lt8912_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; }; display-timings { native-mode = <&timing1>; /* High Definition */ timing0: timing0 { clock-frequency = <74250000>; hactive = <1280>; vactive = <720>; hfront-porch = <110>; hsync-len = <40>; hback-porch = <220>; vfront-porch = <5>; vsync-len = <5>; vback-porch = <20>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; /* Full HD */ timing1: timing1 { clock-frequency = <148500000>; hactive = <1920>; vactive = <1080>; hfront-porch = <88>; hsync-len = <44>; hback-porch = <148>; vfront-porch = <36>; vsync-len = <5>; vback-porch = <4>; hsync-active = <0>; vsync-active = <0>; de-active = <0>; pixelclk-active = <0>; }; }; }; max98089: codec@10 { compatible = "maxim,max98089"; reg = <0x10>; clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; clock-names = "mclk"; vcc-supply = <®_3v3_audio>; dvdd-supply = <®_1v8_ext>; }; }; /* Expansion I2C port bus */ &i2c4 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; pinctrl-1 = <&pinctrl_i2c4_gpio>; scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; &lcdif { status = "okay"; }; /* * Uncomment to enable MCA ADC channels on the XBee Cellular socket: * - MCA_IO1 (channel 1) at XBEE1_UART_TX * - MCA_IO2 (channel 2) at XBEE1_UART_RX * - MCA_IO3 (channel 3) at XBEE1_UART_CTS * - MCA_IO4 (channel 4) at XBEE1_UART_RTS * * These pins are used also by mca_uart2 below. * mca_uart2 must be disabled to be able to use these pins as ADCs. * * Edit adc-ch-list to include the ADC channels that you want to enable. */ // &mca_adc { // digi,adc-ch-list = <1 2 3 4>; // digi,adc-vref = <3000000>; // }; /* * Uncomment to Enable Tamper detection. There are 2 digital (0 and 1) and 2 * analog (2 and 3) tamper interfaces. */ //&mca_tamper { // digi,tamper-if-list = <0 1 2 3>; //}; &mca_uart { status = "okay"; }; /* Assign the IO pins (see bindings) and change status to okay */ &mca_uart0 { iopins-names = "rx", "tx"; iopins = <9 10>; status = "disabled"; }; /* Assign the IO pins (see bindings) and change status to okay */ &mca_uart1 { iopins-names = "rx", "tx"; iopins = <11 16>; status = "disabled"; }; /* UART connected to XBee Cellular socket */ &mca_uart2 { iopins-names = "rx", "tx", "cts", "rts"; iopins = <2 1 3 4>; status = "okay"; }; /* Power LED on MCA_IO13 */ &mca_led { #address-cells = <1>; #size-cells = <0>; status = "okay"; led@0 { reg = <0>; label = "power:green"; io = <13>; linux,default-trigger = "default-on"; retain-state-suspended; }; }; &mipi_csi_1 { #address-cells = <1>; #size-cells = <0>; status = "okay"; /* Camera 0 MIPI CSI-2 (CSIS0) */ port@0 { reg = <0>; mipi_csi0_ep: endpoint { remote-endpoint = <&ov5640_mipi_ep>; data-lanes = <2>; csis-hs-settle = <13>; csis-clk-settle = <2>; csis-wclk; }; csi_mipi_ep: endpoint@2 { remote-endpoint = <&csi_ep>; }; }; }; &mipi_dsi { status = "okay"; #address-cells = <0x1>; #size-cells = <0x0>; port@1 { mipi_dsi_hdmi_out: endpoint { remote-endpoint = <<8912_1_in>; attach-bridge; }; }; port@2 { mipi_dsi_out: endpoint { remote-endpoint = <&bridge_in_dsi>; attach-bridge; }; }; }; &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; status = "okay"; }; /* Conflicts with usbotg2 power enable */ &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; }; /* Conflicts with usbotg2 overcurrent detect */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; status = "disabled"; }; &pcie_phy { fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; status = "okay"; }; &pcie0{ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; disable-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; wake-gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; vpcie-supply = <®_3v3_board>; status = "okay"; }; &sai2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai2>; pinctrl-1 = <&pinctrl_sai2_sleep>; assigned-clocks = <&clk IMX8MM_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; fsl,sai-mclk-direction-output; status = "okay"; }; /* Console */ &uart1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_uart1>; pinctrl-1 = <&pinctrl_uart1_sleep>; status = "okay"; }; /* Expansion port/RS485 UART */ &uart3 { pinctrl-names = "default"; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; /* RS-485 mode (comment these lines to use this UART in RS232 mode) */ pinctrl-0 = <&pinctrl_uart3_rs485>, <&pinctrl_uart3_rs485_re>; linux,rs485-enabled-at-boot-time; rts-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* Disable DMA on this port when using rs485 */ /delete-property/dmas; /delete-property/dma-names; /* * RS-232 mode (uncomment these lines to use this UART in RS232 mode). * (R291, R292 and R359 on the DVK must be removed). */ //fsl,uart-has-rtscts; //pinctrl-0 = <&pinctrl_uart3>; status = "okay"; }; /* XBee 2 UART shared with the Cortex M4 */ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_xbee2_gpios>; assigned-clocks = <&clk IMX8MM_CLK_UART4>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; fsl,uart-has-rtscts; status = "okay"; }; /* USB_OTG1 connected to usb hub */ &usbotg1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1>; vbus-supply = <®_3v3_usb_hub>; dr_mode = "host"; disable-over-current; status = "okay"; }; /* USB_OTG2 connected to usb otg */ &usbotg2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg2>; status = "okay"; }; /* Micro SD card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_vsel>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_vsel>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_vsel>; bus-width = <4>; /* * UHS-I mode (remove the no-1.8-v line to use this uSD in UHS-I mode). * Check schematics for additional hardware changes needed. */ no-1-8-v; cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; status = "okay"; }; &vpu_g1 { status = "okay"; }; &vpu_g2 { status = "okay"; }; &vpu_h1 { status = "okay"; }; &vpu_v4l2 { status = "okay"; }; /* IOMUX */ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; pinctrl_hog: hoggrp { fsl,pins = < /* GPIO1_IO10 on expansion connector */ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 /* GPIO1_IO11 on expansion connector */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 /* User LED 3 */ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x16 /* User button 2 */ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x156 /* * Expansion I2C port IRQ. * Remove if you plan on using this line for a device * connected to the expansion I2C port. */ MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x16 /* * Expansion I2C port GPIO. * Remove if you plan on using this line for a device * connected to the expansion I2C port. */ MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x16 >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 >; }; pinctrl_ecspi3_cs: ecspi3cs { fsl,pins = < MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40000 >; }; pinctrl_fec1_gpio: fec1gpiogrp { fsl,pins = < /* PHY reset */ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 /* PHY interrupt */ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f >; }; pinctrl_flexspi: flexspigrp { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; pinctrl_i2c2_gpio: i2c2grp-gpio { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_i2c3_gpio: i2c3grp-gpio { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 >; }; pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 >; }; pinctrl_i2c4_gpio: i2c4grp-gpio { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 >; }; pinctrl_lt8912: lt8912grp { fsl,pins = < /* Reset */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Interrupt */ MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 >; }; pinctrl_hdmi_hpd: hdmi_hpd_grp { fsl,pins = < /* Hotplug detect */ MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 >; }; pinctrl_lvds: lvdsgrp { fsl,pins = < /* SN65DSI83 enable */ MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* SN65DSI83 interrupt */ MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 >; }; pinctrl_mcp2517fd: mcp2517fdgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 >; }; pinctrl_mipi: mipi { fsl,pins = < /* MIPI_CSI_RESET_N */ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 >; }; pinctrl_pwm2: pwm2grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT 0x16 >; }; pinctrl_pwm4: pwm4grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16 >; }; pinctrl_pcie0: pcie0grp { fsl,pins = < /* Disable GPIO */ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 /* Reset GPIO */ MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x41 /* Wake GPIO */ MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x41 >; }; /* Ethernet PHYs regulator */ pinctrl_reg_3v3_eth0: pinctrl_reg_3v3_eth0grp { fsl,pins = < /* PHY power */ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x41 >; }; pinctrl_reg_5v_board: reg_5v_board_grp { fsl,pins = < /* 5V regulator power enable */ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 >; }; pinctrl_reg_3v3_aud: reg_3v3_aud_grp { fsl,pins = < /* Audio power enable */ MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x41 >; }; pinctrl_reg_3v3_usb_hub: reg_3v3_usb_hub_grp { fsl,pins = < /* GPIO3_25 USB hub power enable */ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41 >; }; pinctrl_reg_3v3_board: reg_3v3_board_grp { fsl,pins = < /* GPIO3_19 board regulator enable */ MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 >; }; pinctrl_sai2_sleep: sai2sleepgrp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x100 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x100 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x100 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x100 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x100 >; }; pinctrl_touch: touchgrp { fsl,pins = < /* LVDS touch interrupt */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 >; }; pinctrl_uart1_sleep: uart1sleepgrp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x100 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x100 >; }; pinctrl_uart3: uart3grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 >; }; pinctrl_uart3_rs485: uart3_rs485grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 >; }; pinctrl_uart3_rs485_re: uart3_rs485grp_re { fsl,pins = < /* RS485 RE#/DE line */ MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x16 >; }; pinctrl_uart4: uart4grp { fsl,pins = < MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 >; }; pinctrl_usbotg1: usbotg1grp { fsl,pins = < /* USB hub reset */ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 >; }; pinctrl_usbotg2: usbotg2grp { fsl,pins = < /* USB otg2 power enable */ MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16 /* USB otg2 overcurrent detect */ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x16 >; }; pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < /* Card detect */ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 >; }; pinctrl_usdhc2_vsel: usdhc2grp_vsel { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 >; }; pinctrl_xbee2_gpios: xbee2grp { fsl,pins = < /* XBEE_RESET_N */ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 /* XBEE_ON/SLEEP_N */ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* XBEE_SLEEP_RQ */ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 >; }; };