/*----------------------------------------------------------------------------*/
/* sys_link.cmd                                                               */
/*                                                                            */
/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
* 
* 
*  Redistribution and use in source and binary forms, with or without 
*  modification, are permitted provided that the following conditions 
*  are met:
*
*    Redistributions of source code must retain the above copyright 
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the 
*    documentation and/or other materials provided with the   
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/

/*                                                                            */
/*----------------------------------------------------------------------------*/
/* USER CODE BEGIN (0) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Linker Settings                                                            */

--retain="*(.intvecs)"

/* USER CODE BEGIN (1) */
#if 0
/* NOTE: the default memory mapy is created by HALCoGen and it starts from 0x00000000
   The memory map cannot be changed in HALCoGen so the memory map that starts from
   0x00010000 shall be created directly in sys_link.cmd below. So #if 1 and #if 0 were
   added to disregard the auto generated memroy map. The edited memory map should
   be in the user defined code to map sure it is not removed every time HALCoGen is
   created.
*/
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Memory Map                                                                 */

MEMORY
{
    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
    STACKS  (RW) : origin=0x08000000 length=0x00003400
    RAM     (RW) : origin=0x08003400 length=0x0002cc00

/* USER CODE BEGIN (2) */
#endif
/* Override Memory Segments with CRC here */
MEMORY
{
    VECTORS (X)  : origin=0x00010000
                   length=0x00000020
                   vfill = 0xffffffff

    CRCMEM  (RX) : origin=end(VECTORS)
                   length=0x000001E0
                   vfill = 0xffffffff

    FLASH0  (RX) : origin=end(CRCMEM)
                   length=(0x0013FFFF - end(CRCMEM))
                   vfill = 0xffffffff

    STACKS  (RW) : origin=0x08000000
                   length=0x00004c00

    RAM     (RW) : origin=0x08004c00
                   length=0x0002b400
/* USER CODE END */
}

/* USER CODE BEGIN (3) */
#if 0
/* NOTE: the default section has been disabled to run crc check of the image
   in the user defined section below.
*/
/* USER CODE END */

/*----------------------------------------------------------------------------*/
/* Section Configuration                                                      */

SECTIONS
{
    .intvecs : {} > VECTORS
    .text    : {} > FLASH0 
    .const   : {} > FLASH0 
    .cinit   : {} > FLASH0 
    .pinit   : {} > FLASH0 
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
    

/* USER CODE BEGIN (4) */
#endif
/* Override Sections with CRCs here */
SECTIONS
{
    .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
    .text    : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .const   : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .cinit   : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C )
    .pinit   : {} > FLASH0
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM

    .TI.crctab : {} > CRCMEM
/* USER CODE END */
}

/* USER CODE BEGIN (5) */
/* USER CODE END */


/*----------------------------------------------------------------------------*/
/* Misc                                                                       */

/* USER CODE BEGIN (6) */
/* USER CODE END */
/*----------------------------------------------------------------------------*/