/**************************************************************************
*
* Copyright (c) 2021-2025 Diality Inc. - All Rights Reserved.
*
* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
*
* @file    Voltages.h
*
* @author  (last)      Dara Navaei
* @date    (last)      24-Aug-2023
*
* @author  (original)  Sean Nash
* @date    (original)  21-Apr-2021
*
***************************************************************************/

#ifndef __VOLTAGES_H__
#define __VOLTAGES_H__

#include "DGCommon.h"

/**
 *  @defgroup Voltages Voltages
 *  @brief Voltages monitor module.  Monitors the various system voltages
 *  to ensure they are in expected range.
 *
 *  @addtogroup Voltages
 *  @{
 */

// ********** public definitions **********

/// Enumeration of voltages monitored by this module.
typedef enum Voltages
{
    MONITORED_LINE_24V_MAIN = 0,                                                ///< First voltage in list
    MONITORED_LINE_FIRST_VOLTAGE = MONITORED_LINE_24V_MAIN,                     ///< Main voltage (24V) (non-isolated)
    MONITORED_LINE_1_8V_FPGA,                                                   ///< FPGA logic voltage (1.8V)
    MONITORED_LINE_1V_FPGA,                                                     ///< FPGA reference voltage (1V)
    MONITORED_LINE_3_3V_SENSORS,                                                ///< Sensors voltage (3.3V)
    MONITORED_LINE_1_8V_PROC,                                                   ///< Processor voltage (1.8V)
    MONITORED_LINE_5V_SENSORS,                                                  ///< Sensors voltage (5V)
    MONITORED_LINE_5V_LOGIC,                                                    ///< Logic voltage (5V)
    MONITORED_LINE_3_3V,                                                        ///< Logic voltage (3.3V)
    MONITORED_LINE_1_2V_PROC,                                                   ///< Processor voltage (1.2V)
    MONITORED_LINE_V_REF,                                                       ///< Reference voltage (3V)
    MONITORED_LINE_EXT_ADC_1_REF_V,                                             ///< External ADC 1 reference voltage (3V)
    MONITORED_LINE_EXT_ADC_2_REF_V,                                             ///< External ADC 2 reference voltage (3V)
    MONITORED_LINE_FPGA_VCC_V,                                                  ///< FPGA input voltage (3V)
    MONITORED_LINE_FPGA_AUX_VCC_V,                                              ///< FPGA auxiliary Vcc voltage (3V)
    MONITORED_LINE_FPGA_VPVN_V,                                                 ///< FPGA VPVN voltage (1V)
    MONITORED_LINE_PS_GATE_DRIVER_V,                                            ///< P/S gate driver voltage (5V)
    MONITORED_LINE_NON_ISOLATED_24_V_MAIN,                                      ///< Non-isolated
    MONITORED_LINE_24V_POWER_PRIM_HTR_V,                                        ///< Primary heater voltage (24V) (isolated)
    MONITORED_LINE_LAST_RANGE_CHECKED_LINE = MONITORED_LINE_24V_POWER_PRIM_HTR_V,   ///< The last monitored line that is checked per fixed range.
    MONITORED_LINE_24V_GND_MAIN_PRIM_HTR_V,                                     ///< Main primary heater ground voltage (24V when off, <5V when on)
    MONITORED_LINE_24V_GND_SMALL_PRIM_HTR_V,                                    ///< Small primary heater voltage (24V)
    MONITORED_LINE_24V_GND_TRIM_HTR_V,                                          ///< Trimmer heater voltage (24V)
    NUM_OF_MONITORED_LINES                                                      ///< Number of monitored voltages
} MONITORED_VOLTAGES_T;

/// Payload record structure for the voltages data message.
typedef struct
{
    F32 adc1VFPGA;                                                              ///< Internal ADC channel for 1V FPGA reference
    F32 adc1_2VProc;                                                            ///< Internal ADC channel for 1.2V to processor
    F32 adc1_8VProc;                                                            ///< Internal ADC channel for 1.8V to processor
    F32 adc1_8VFPGA;                                                            ///< Internal ADC channel for 1.8V to FPGA
    F32 adc3VRef;                                                               ///< Internal ADC channel for 3V reference
    F32 adc3VExtADC1;                                                           ///< Internal ADC channel for 3V reference to external ADC 1
    F32 adc3VExtADC2;                                                           ///< Internal ADC channel for 3V reference to external ADC 2
    F32 adc3_3V;                                                                ///< Internal ADC channel for 3.3V
    F32 adc3_3VSensors;                                                         ///< Internal ADC channel for 3.3V to sensors
    F32 adc5VLogic;                                                             ///< Internal ADC channel for 5V to logic
    F32 adc5VSensors;                                                           ///< Internal ADC channel for 5V to sensors
    F32 adc5VPSGateDriver;                                                      ///< Internal ADC channel for 5V P/S gate driver
    F32 adc24V;                                                                 ///< Internal ADC channel for 24V
    F32 adc24VPowerPrimHtr;                                                     ///< FPGA ADC channel for 24V to primary heater
    F32 adc24VGndMainPrimHtr;                                                   ///< FPGA ADC channel for 24V to primary heater
    F32 adc24VGndSmallPrimHtr;                                                  ///< Internal ADC channel for 24V to secondary heater
    F32 adc24VGndTrimmerHtr;                                                    ///< Internal ADC channel for 24V to trimmer heater
    F32 fpgaIntVCC;                                                             ///< FPGA internal VCC for 1V
    F32 fpgaAuxVCC;                                                             ///< FPGA auxiliary VCC for 1.8V
    F32 fpgaVPVN;                                                               ///< FPGA VPVN for 0V
    F32 acdNonIsolated24V;                                                      ///< Internal ADC channel for the non-isloated 24V
} VOLTAGES_DATA_PAYLOAD_T;

// ********** public function prototypes **********

void initVoltagesMonitor( void );
void execVoltagesMonitor( void );

F32 getMonitoredLineLevel( MONITORED_VOLTAGES_T signal );
F32 getRawIsolatedPowerSupplyVoltage( void );

BOOL testSetVoltagesDataPublishIntervalOverride( U32 value );
BOOL testResetVoltagesDataPublishIntervalOverride( void );
BOOL testSetLineLevelOverride( U32 signal, F32 value );
BOOL testResetLineLevelOverride( U32 signal );

/**@}*/

#endif