-- VectorCAST 19 revision c2818cf (09/24/19) -- Test Case Script -- -- Environment : FPGA -- Unit(s) Under Test: FPGA -- -- Script Features TEST.SCRIPT_FEATURE:C_DIRECT_ARRAY_INDEXING TEST.SCRIPT_FEATURE:CPP_CLASS_OBJECT_REVISION TEST.SCRIPT_FEATURE:MULTIPLE_UUT_SUPPORT TEST.SCRIPT_FEATURE:MIXED_CASE_NAMES TEST.SCRIPT_FEATURE:STATIC_HEADER_FUNCS_IN_UUTS TEST.SCRIPT_FEATURE:VCAST_MAIN_NOT_RENAMED -- -- Unit: FPGA -- Subprogram: consumeUnexpectedData -- Test Case: DataBytePending TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:DataBytePending TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:1 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady uut_prototype_stubs.sciReceiveByte FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Test Case: NoData TEST.UNIT:FPGA TEST.SUBPROGRAM:consumeUnexpectedData TEST.NEW TEST.NAME:NoData TEST.VALUE:uut_prototype_stubs.sciIsRxReady.return:0 TEST.FLOW FPGA.c.consumeUnexpectedData uut_prototype_stubs.sciRxError uut_prototype_stubs.sciIsRxReady FPGA.c.consumeUnexpectedData TEST.END_FLOW TEST.END -- Subprogram: execFPGAIn -- Test Case: CommErrorTooManyRetries TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:CommErrorTooManyRetries TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaCommRetryCount:5 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:6 TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:InvalidState TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: OutgoingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:OutgoingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Test Case: RcvAllSensorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvAllSensorsState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[11]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[12]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[13]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[14]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[15]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[16]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[19]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[20]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[21]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[22]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[23]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[24]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[25]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[26]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[27]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[28]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[29]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[30]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[31]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[32]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[33]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[34]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[35]:0x34 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[36]:0x12 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0x201 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0x6050403 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0x90807 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0x4030201 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0x8070605 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0x2010009 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0x6050403 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0x90807 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0x4030201 TEST.EXPECTED:uut_prototype_stubs.crc16.len:35 TEST.END -- Test Case: RcvHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:RcvHeaderState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:<> TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaDiag:0 TEST.VALUE:FPGA.<>.fpgaHeader.gap1:0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:0x0 TEST.VALUE:FPGA.<>.fpgaHeader.fpgaControl:0x0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCmdBuffer:"0" TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaId:1 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaRev:2 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaDiag:3 TEST.EXPECTED:FPGA.<>.fpgaHeader.gap1:4 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaStatus:0x605 TEST.EXPECTED:FPGA.<>.fpgaHeader.fpgaControl:0x807 TEST.END -- Test Case: StartState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAIn TEST.NEW TEST.NAME:StartState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_START TEST.VALUE:FPGA.<>.fpgaReceiptCounter:1 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:1 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.END -- Subprogram: execFPGAOut -- Test Case: FailedState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:FailedState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_FAILED TEST.END -- Test Case: IncomingState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:IncomingState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.END -- Test Case: InvalidState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:InvalidState TEST.VALUE:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.EXPECTED:FPGA.<>.fpgaState:NUM_OF_FPGA_STATES TEST.END -- Test Case: ReadHeaderState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:ReadHeaderState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_HEADER TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:8 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:11 TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.END -- Test Case: WriteAllActuatorsState TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGAOut TEST.NEW TEST.NAME:WriteAllActuatorsState TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.VALUE:FPGA.<>.fpgaReceiptCounter:0 TEST.VALUE:FPGA.<>.fpgaTransmitCounter:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaReadCommandInProgress:0 TEST.VALUE:FPGA.<>.fpgaBulkWriteAndReadInProgress:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[0]:0x55 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[1]:2 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaWriteCmdBuffer[3]:1 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaReceiptCounter:0 TEST.EXPECTED:FPGA.<>.fpgaTransmitCounter:0 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandInProgress:0 TEST.EXPECTED:FPGA.<>.fpgaBulkWriteAndReadInProgress:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:8 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0x0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0x0 TEST.EXPECTED:uut_prototype_stubs.crc16.len:5,4 TEST.END -- Subprogram: execFPGATest -- Test Case: TestFailed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestFailed TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x58 TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_FAILED TEST.END -- Test Case: TestPassed TEST.UNIT:FPGA TEST.SUBPROGRAM:execFPGATest TEST.NEW TEST.NAME:TestPassed TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x59 TEST.EXPECTED:FPGA.execFPGATest.return:SELF_TEST_STATUS_PASSED TEST.END -- Subprogram: getFPGADiag -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGADiag TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaDiag:0x68 TEST.EXPECTED:FPGA.getFPGADiag.return:0x68 TEST.END -- Subprogram: getFPGAId -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAId TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaId:0x59 TEST.EXPECTED:FPGA.getFPGAId.return:0x59 TEST.END -- Subprogram: getFPGARev -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGARev TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaRev:1 TEST.EXPECTED:FPGA.getFPGARev.return:1 TEST.END -- Subprogram: getFPGAStatus -- Test Case: NominalPath TEST.UNIT:FPGA TEST.SUBPROGRAM:getFPGAStatus TEST.NEW TEST.NAME:NominalPath TEST.VALUE:FPGA.<>.fpgaHeader.fpgaStatus:0x1234 TEST.EXPECTED:FPGA.getFPGAStatus.return:0x1234 TEST.END -- Subprogram: handleFPGAReadHeaderState -- Test Case: NominalCase TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReadHeaderState TEST.NEW TEST.NAME:NominalCase TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[0]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[3]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[4]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[5]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.VALUE:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.VALUE:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:0 TEST.VALUE:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_READ_HEADER TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[0]:0x5A TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[1]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[2]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[3]:8 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[4]:0x34 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[5]:0x12 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[6]:0 TEST.EXPECTED:FPGA.<>.fpgaReadCmdBuffer[7]:0 TEST.EXPECTED:FPGA.<>.fpgaDMAReadControlRecord.FRCNT:6 TEST.EXPECTED:FPGA.<>.fpgaDMAReadRespControlRecord.FRCNT:11 TEST.EXPECTED:FPGA.handleFPGAReadHeaderState.return:FPGA_STATE_RCV_HEADER TEST.EXPECTED:uut_prototype_stubs.crc16.len:4 TEST.END -- Subprogram: handleFPGAReceiveAllSensorsState -- Test Case: BadCRC TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:BadCRC TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xAA TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[1]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[2]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[3]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[4]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[5]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[6]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[7]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[8]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[9]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[10]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[11]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[12]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[13]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[14]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[15]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[16]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[17]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[18]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[19]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[20]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[21]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[22]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[23]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[24]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[25]:5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[26]:6 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[27]:7 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[28]:8 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[29]:9 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[30]:0 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[31]:1 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[32]:2 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[33]:3 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[34]:4 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[35]:0x12 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[36]:0x34 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 TEST.VALUE:uut_prototype_stubs.crc16.return:0x1234 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0x0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.EXPECTED:uut_prototype_stubs.crc16.len:35 TEST.END -- Test Case: NAKResponse TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NAKResponse TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaReadResponseBuffer[0]:0xEF TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.venousPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.arterialPressure:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2a:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 TEST.EXPECTED:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.EXPECTED:FPGA.<>.fpgaCommRetryCount:1 TEST.EXPECTED:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaReadCommandResponseReceived:1 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.bloodLeak:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp1:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.venousPressure:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.arterialPressure:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc1a:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.adc2a:0 TEST.EXPECTED:FPGA.<>.fpgaSensorReadings.dialysateTemp2:0 TEST.EXPECTED:FPGA.handleFPGAReceiveAllSensorsState.return:FPGA_STATE_WRITE_ALL_ACTUATORS TEST.END -- Test Case: NoResponseReceived TEST.UNIT:FPGA TEST.SUBPROGRAM:handleFPGAReceiveAllSensorsState TEST.NEW TEST.NAME:NoResponseReceived TEST.VALUE:FPGA.<>.fpgaState:FPGA_STATE_RCV_ALL_SENSORS TEST.VALUE:FPGA.<>.fpgaCommRetryCount:0 TEST.VALUE:FPGA.<>.fpgaWriteCommandResponseReceived:1 TEST.VALUE:FPGA.<>.fpgaReadCommandResponseReceived:0 TEST.VALUE:FPGA.<>.fpgaWriteResponseBuffer[0]:0xA5 TEST.VALUE:FPGA.<>.fpgaSensorReadings.bloodLeak:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc1b:0 TEST.VALUE:FPGA.<>.fpgaSensorReadings.adc2b:0 TEST.VALUE:FPGA.<