/************************************************************************** * * Copyright (c) 2020-2024 Diality Inc. - All Rights Reserved. * * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. * * @file HDCommon.h * * @author (last) Dara Navaei * @date (last) 06-Feb-2024 * * @author (original) Sean * @date (original) 27-Feb-2020 * ***************************************************************************/ #ifndef __HD_COMMON_H__ #define __HD_COMMON_H__ #include "hal_stdtypes.h" // ********** version ********** #define HD_VERSION_MAJOR 1 #define HD_VERSION_MINOR 0 #define HD_VERSION_MICRO 0 #define HD_VERSION_BUILD 32 // ********** development build switches ********** #ifndef _RELEASE_ #ifndef _VECTORCAST_ // Build switches. NOTE: These build switches are never considered for release builds. // #define BOARD_WITH_NO_HARDWARE 1 // Target is a PCB w/ no hardware // #define SIMULATE_UI 1 // Build w/o requirement that UI be there // #define TASK_TIMING_OUTPUT_ENABLED 1 // Re-purposes alarm lamp pins for task timing #include #include #endif #endif #include "Common.h" /** * @defgroup CommonHDHeader CommonHDHeader * @brief Provides commonly used definitions and macros for HD firmware. * * @addtogroup CommonHDHeader * @{ */ // **** Common Definitions **** #pragma pack(push,1) /// Payload record structure for an HD versions message. typedef struct { U08 major; ///< HD version major revision. U08 minor; ///< HD version minor revision. U08 micro; ///< HD version micro revision. U16 build; ///< HD build version. U08 fpgaId; ///< HD FPGA ID. U08 fpgaMajor; ///< HD FPGA major revision. U08 fpgaMinor; ///< HD FPGA minor revision. U08 fpgaLab; ///< HD FPGA lab revision. U32 compatibilityRev; ///< HD compatibility revision. } HD_VERSIONS_T; /// DG version struct. typedef struct { U08 major; ///< DG version major revision. U08 minor; ///< DG version major revision. U08 micro; ///< DG version micro revision. U16 build; ///< DG build version. U08 fpgaId; ///< DG FPGA ID. U08 fpgaMajor; ///< DG FPGA major revision. U08 fpgaMinor; ///< DG FPGA minor revision. U08 fpgaLab; ///< DG FPGA lab revision. U32 compatibilityRev; ///< DG compatibility revision. } DG_VERSIONS_T; /// Record defining the fields in a UI version request message. typedef struct { U08 major; ///< Major version for UI software. U08 minor; ///< Minor version for UI software. U08 micro; ///< Micro version for UI software. U16 build; ///< Build number for UI software. U32 compatibility; ///< Compatibility revision. } UI_VERSIONS_T; /// Payload record structure for a peristaltic pump data message. typedef struct { U32 setPoint; ///< Set point. F32 measFlow; ///< Measured flow in mL/min. F32 measRotorSpd; ///< Measured rotor speed in RPM. F32 measPumpSpd; ///< Measured pump speed in RPM. F32 measMCSpd; ///< Measured motor speed in RPM. F32 measMCCurr; ///< Measured motor current in Amps. F32 pwmDC; ///< Duty cycle. } PERISTALTIC_PUMP_STATUS_PAYLOAD_T; /// Payload record structure for a pump set point override message. typedef struct { BOOL reset; ///< Reset. S32 setPt; ///< Set point. U32 ctrlMode; ///< Control mode. } OVERRIDE_PUMP_SET_PT_PAYLOAD_T; #pragma pack(pop) // **** Common Macros **** /**@}*/ // **** VectorCAST Definitions **** #ifdef _VECTORCAST_ #endif #endif