/*
 * Common.h
 *
 *  Created on: Aug 5, 2024
 *      Author: fw
 */

#ifndef __COMMON_H__
#define __COMMON_H__

#define FIRMWARE_START_ADDRESS                0x00010000
#define FIRMWARE_CRC_TABLE_ADDRESS            0x10020             ///< The starting address of CRC table for firmware image.
#define SW_UPDATE_FLASH_BUFFER_SIZE           128
#define MASK_OFF_MSB                          0x00FF      ///< Bits to mask off the most significant byte of a 2-byte word
#define MASK_OFF_LSB                          0xFF00      ///< Bits to mask off the least significant byte of a 2-byte word
#define SHIFT_8_BITS_FOR_BYTE_SHIFT           8           ///< Number of bits to shift in order to shift a byte

// **** Types ****

typedef float                    F32;               ///< 32-bit floating point type
typedef double                   F64;               ///< 64-bit floating point type
typedef long long                S64;               ///< 64-bit signed integer type
typedef unsigned int             U32;               ///< 32-bit unsigned integer type
typedef int                      S32;               ///< 32-bit signed integer type
typedef unsigned short           U16;               ///< 16-bit unsigned integer type
typedef short                    S16;               ///< 16-bit signed integer type
typedef unsigned char            U08;               ///< 8-bit unsigned integer type
typedef unsigned int             BOOL;              ///< 32-bit boolean type
typedef unsigned char            BYTE;              ///< 8-bit byte type

typedef enum BL_Op_Modes
{
    MODE_STAND = 0,
    MODE_UPDATE,
    NUM_OF_MODES
} BL_OP_MODE_T;

typedef enum SW_Mode_Standby_States
{
    STANDBY_CHECK_FOR_UPDATE_STATE = 0,
    STANDBY_CHECK_FW_AND_FPGA_IMAGES_STATE,
    STANDBY_IDLE_STATE,
    NUM_OF_MODE_STANDBY_STATES
} MODE_STANDBY_STATE_T;

typedef enum SW_Mode_Update_States
{
    SW_UPDATE_UPDATE_STATE = 0,
    SW_UPDATE_VERIFY_STATE,
    SW_UPDATE_ABORT_STATE,
    NUM_OF_MODE_SW_UPDATE_STATES
} MODE_SW_UPDATE_STATE_T;

typedef enum SW_Update_Destinations
{
    UPDATE_FIRMWARE = 0,
    UPDATE_FPGA,
    NUM_OF_UPDATE_DESTS
} SW_UPDATE_DESINTATION_T;

typedef enum SW_Update_CAN_Mail_Boxes
{
    SW_UPDATE_NOT_USED = 0,
    SW_UPDATE_COMMAD,
    SW_UPDATE_TD_UPDATE,
    SW_UPDATE_DD_UPDATE,
    SW_UPDATE_RO_UPDATE,
    PLACE_HOLDER_TO_REMOVE_CAN,
    SW_UPDATE_RESP,
    NUM_OF_SW_UPDATE_MBOXES,
} SW_UPDATE_CAN_MAIL_BOX_T;

/*!
Normal Protocol:
    UI->FW: SwUpdateCommand[cmd=start]
    FW->UI: Secure Ack/Nack
    loop
      UI->FW: Data
      FW->UI: Secure Ack/Nack  <- Also flow control.
    end

    UI->FW: Verify
    FW->UI: SwUpdateVerifyResponse

    UI->FW: Version
    FW->UI: SwUpdateVerifyResponse

    UI->FW: Verified UI thinks things are good.
    FW->UI: ACK/NACK FW has agreed or not and set the FLASH memory that the image is good or not.

    UI->FW: RunApp Launch the main app.
    FW->UI: Secure Ack/Nack

    If streaming encounters problems we use a command with Resync
    so that the FW will dump it's indexes and be ready for new data.
*/
typedef enum SW_Update_Commands
{
    UPDATE_CMD_START = 0,
    UPDATE_CMD_ABORT,
    UPDATE_CMD_RUNAPP,  // TODO is this needed?
    UPDATE_CMD_VERIFY,
    UPDATE_CMD_VERSION,  // TODO is this needed?
    UPDATE_CMD_VERIFIED,
    UPDATE_CMD_RESYNC,
    UPDATE_CMD_IDLE,
    NUM_OF_UPDATE_CMDS
} SW_UPDATE_CMD_T;

typedef enum Ack_Nack
{
    NACK = 0,
    ACK,
    NUM_OF_ACK_NACK
} ACK_NACK_STATUS_T;


typedef struct
{
    BOOL isSWUpdateBufferReady;
    SW_UPDATE_DESINTATION_T dest;
} SW_UPDATE_BUFFER_STATUS_T;

typedef struct
{
    U08 msgID;
    U08 updateCmd;
    U16 cyberRandom;
    U32 msgCRC;
} SW_UPDATE_CMD_STATUS_T;

#endif