Testcase Management Report
Configuration Data
| Environment Name | FPGA |
|---|
| Date of Report Creation | 01 NOV 2019 |
|---|
| Time of Report Creation | 8:18:45 AM |
|---|
| Testcases |
51 / 51 PASS |
| Expecteds |
514 / 514 PASS |
| Control Flow |
9 / 9 PASS |
| Statement Coverage |
231 / 231 (100%) |
| Branch Coverage |
112 / 112 (100%) |
| Pairs Coverage |
20 / 20 (100%) |
| Unit | Subprogram | Test Cases | Execution Date and Time | Pass/Fail |
| FPGA | initFPGA | NominalPath | 01 NOV 2019 8:08:25 AM | PASS 107 / 107 |
| | resetFPGACommFlags | NominalPath | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
| | signalFPGAReceiptCompleted | BulkWriteAndReadInProgressAfterWrite | 01 NOV 2019 8:08:25 AM | PASS 11 / 11 |
| | | NothingInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
| | | ReadCmdInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
| | | WriteCmdInProgress | 01 NOV 2019 8:08:25 AM | PASS 7 / 7 |
| | signalFPGATransmitCompleted | NominalPath | 01 NOV 2019 8:08:26 AM | PASS 7 / 7 |
| | execFPGAIn | CommErrorTooManyRetries | 01 NOV 2019 8:08:26 AM | PASS 9 / 9 |
| | | FailedState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
| | | InvalidState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
| | | OutgoingState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
| | | RcvAllSensorsState | 01 NOV 2019 8:10:05 AM | PASS 19 / 19 |
| | | RcvHeaderState | 01 NOV 2019 8:08:26 AM | PASS 15 / 15 |
| | | StartState | 01 NOV 2019 8:08:26 AM | PASS 8 / 8 |
| | execFPGAOut | FailedState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
| | | IncomingState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
| | | InvalidState | 01 NOV 2019 8:08:27 AM | PASS 1 / 1 |
| | | ReadHeaderState | 01 NOV 2019 8:08:27 AM | PASS 19 / 19 |
| | | WriteAllActuatorsState | 01 NOV 2019 8:08:27 AM | PASS 18 / 18 |
| | handleFPGAReadHeaderState | NominalCase | 01 NOV 2019 8:08:27 AM | PASS 13 / 13 |
| | handleFPGAReceiveHeaderState | BadCRC | 01 NOV 2019 8:08:27 AM | PASS 11 / 11 |
| | | NAKResponse | 01 NOV 2019 8:08:27 AM | PASS 10 / 10 |
| | | NoResponseReceived | 01 NOV 2019 8:08:28 AM | PASS 10 / 10 |
| | | NominalCase | 01 NOV 2019 8:08:28 AM | PASS 11 / 11 |
| | handleFPGAWriteAllActuatorsState | NominalPath | 01 NOV 2019 8:08:28 AM | PASS 25 / 25 |
| | handleFPGAReceiveAllSensorsState | BadCRC | 01 NOV 2019 8:16:16 AM | PASS 15 / 15 |
| | | NAKResponse | 01 NOV 2019 8:16:46 AM | PASS 14 / 14 |
| | | NoResponseReceived | 01 NOV 2019 8:17:21 AM | PASS 14 / 14 |
| | | NominalPath | 01 NOV 2019 8:08:28 AM | PASS 14 / 14 |
| | | NoWriteResponseReceived | 01 NOV 2019 8:18:36 AM | PASS 14 / 14 |
| | execFPGATest | TestFailed | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | | TestPassed | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | setupDMAForWriteCmd | LengthTooLarge | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | startDMAWriteCmd | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 20 / 20 |
| | setupDMAForWriteResp | LengthTooLarge | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 1 / 1 |
| | startDMAReceiptOfWriteResp | NominalPath | 01 NOV 2019 8:08:29 AM | PASS 20 / 20 |
| | setupDMAForReadCmd | LengthTooLarge | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
| | | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
| | startDMAReadCmd | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 20 / 20 |
| | setupDMAForReadResp | LengthTooLarge | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
| | | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
| | startDMAReceiptOfReadResp | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 20 / 20 |
| | getFPGAId | NominalPath | 01 NOV 2019 8:08:30 AM | PASS 1 / 1 |
| | getFPGARev | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
| | getFPGADiag | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
| | getFPGAStatus | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
| | setFPGAControl | NominalPath | 01 NOV 2019 8:08:31 AM | PASS 1 / 1 |
| | consumeUnexpectedData | DataBytePending | 01 NOV 2019 8:08:31 AM | PASS |
| | | NoData | 01 NOV 2019 8:08:31 AM | PASS |
| TOTALS | 25 | 51 | | PASS 51 / 51 |
|---|
Statement+MC/DC
| Unit | Subprogram | Complexity | Statements | Branches | Pairs |
| FPGA | initFPGA | 1 | 79 / 79 (100%) | 1 / 1 (100%) | |
| | resetFPGACommFlags | 1 | 7 / 7 (100%) | 1 / 1 (100%) | |
| | signalFPGAReceiptCompleted | 4 | 12 / 12 (100%) | 13 / 13 (100%) | 3 / 3 (100%) |
| | signalFPGATransmitCompleted | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | execFPGAIn | 7 | 17 / 17 (100%) | 14 / 14 (100%) | 2 / 2 (100%) |
| | execFPGAOut | 5 | 12 / 12 (100%) | 9 / 9 (100%) | 1 / 1 (100%) |
| | handleFPGAReadHeaderState | 1 | 14 / 14 (100%) | 1 / 1 (100%) | |
| | handleFPGAReceiveHeaderState | 4 | 15 / 15 (100%) | 13 / 13 (100%) | 3 / 3 (100%) |
| | handleFPGAWriteAllActuatorsState | 1 | 25 / 25 (100%) | 1 / 1 (100%) | |
| | handleFPGAReceiveAllSensorsState | 5 | 17 / 17 (100%) | 19 / 19 (100%) | 5 / 5 (100%) |
| | execFPGATest | 2 | 4 / 4 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| | setupDMAForWriteCmd | 2 | 2 / 2 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| | startDMAWriteCmd | 1 | 3 / 3 (100%) | 1 / 1 (100%) | |
| | setupDMAForWriteResp | 2 | 2 / 2 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| | startDMAReceiptOfWriteResp | 1 | 3 / 3 (100%) | 1 / 1 (100%) | |
| | setupDMAForReadCmd | 2 | 2 / 2 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| | startDMAReadCmd | 1 | 3 / 3 (100%) | 1 / 1 (100%) | |
| | setupDMAForReadResp | 2 | 2 / 2 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| | startDMAReceiptOfReadResp | 1 | 3 / 3 (100%) | 1 / 1 (100%) | |
| | getFPGAId | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | getFPGARev | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | getFPGADiag | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | getFPGAStatus | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | setFPGAControl | 1 | 1 / 1 (100%) | 1 / 1 (100%) | |
| | consumeUnexpectedData | 2 | 3 / 3 (100%) | 5 / 5 (100%) | 1 / 1 (100%) |
| TOTALS | 25 | 51 | 231 / 231 (100%) | 112 / 112 (100%) | 20 / 20 (100%) |
| GRAND TOTALS | 25 | 51 | 231 / 231 (100%) | 112 / 112 (100%) | 20 / 20 (100%) |
