Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r012573b1913d1bfd2357acfadcad6bb20b295ad9 -ra5cbf07811efee3c038a550f251d3daefff2bf63 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision a5cbf07811efee3c038a550f251d3daefff2bf63) @@ -11,6 +11,7 @@ #include "sys_dma.h" #include "Comm.h" +#include "Download.h" #include "FPGA.h" #include "Timers.h" #include "Utilities.h" @@ -38,9 +39,10 @@ #define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. #define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO does this vary? #define FPGA_FLASH_CONTROL_REG_ADDR 0x090E -#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. -#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. -#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. +#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe +#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe +#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe +#define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. #define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) @@ -76,9 +78,7 @@ FPGA_RESET_FLASH, FPGA_ERASE_FIFO, FPGA_ENABLE_FLASH, - FPGA_CHECK_ERASE_FIFO_STATUS, - FPGA_CHECK_FLASH_READY_STATUS, - FPGA_CHECK_FIFO_COUNT, + FPGA_READ_MULTI_BOOT_STATUS, FPGA_FLASH_WRITE_DATA, FPGA_SELF_CONFIGURE, NUM_OF_FPGA_JOBS, @@ -117,6 +117,7 @@ typedef struct { BOOL isFlashErased; + U16 fifoRemainingCount; FPGA_FLASH_STATE_T fpgaFlashState; U32 startTime; } FPGA_FLASH_STATUS_T; @@ -153,6 +154,9 @@ static U32 fpgaDataLenToWrite; static U32 TESTREMOVE = 0; // TODO remove +static U32 countRemove = 0; // TODO remove +static U32 nonzeroCounter = 0; // TODO remove +static U16 nonZeroCount[100]; // TODO remove static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF }; // TODO update with the real FPGA IDs static const U16 DISABLE_UPDATE_REG_CMD = 5; // TODO what is this value? 0? @@ -168,19 +172,15 @@ { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH - { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_ERASE_FIFO_STATUS - { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FLASH_READY_STATUS - { FPGA_FIFO_COUNT_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FIFO_COUNT + { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( U32 ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; static void initDMA( void ); static void consumeUnexpectedData( void ); static BOOL processFPGAReceivedData( void ); -static BOOL isFPGAEraseFlashStatusOk( void ); -static BOOL isFPGAFlashStatusOk( void ); -static BOOL isFPGAFIFOStatusOk( void ); +static void processFPGAFlashStatus( void ); static void setupDMAForReadResp( U32 bytes2Receive ); static void setupDMAForReadCmd( U32 bytes2Transmit ); @@ -215,6 +215,7 @@ enqueue( FPGA_READ_HEADER ); enqueue( FPGA_READ_UPDATE_REG ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); fpgaState = FPGA_IDLE_STATE; fpgaUpdateRegisterStatus = 0; @@ -295,10 +296,9 @@ { if ( FALSE == isQueueFull() ) { - //enqueue( FPGA_RESET_FLASH ); - //enqueue( FPGA_ERASE_FIFO ); + enqueue( FPGA_RESET_FLASH ); + enqueue( FPGA_ERASE_FIFO ); enqueue( FPGA_ENABLE_FLASH ); - //enqueue( FPGA_CHECK_ERASE_FIFO_STATUS ); } } @@ -308,12 +308,8 @@ { memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); - //enqueue( FPGA_CHECK_FLASH_READY_STATUS ); - //enqueue( FPGA_CHECK_FIFO_COUNT ); enqueue( FPGA_FLASH_WRITE_DATA ); - //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + fpgaDataLenToWrite = len; memcpy( fpgaDataToWriteBuffer, data, len ); @@ -448,18 +444,10 @@ fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; break; - case FPGA_CHECK_ERASE_FIFO_STATUS: - status = isFPGAEraseFlashStatusOk(); + case FPGA_READ_MULTI_BOOT_STATUS: + processFPGAFlashStatus(); break; - case FPGA_CHECK_FLASH_READY_STATUS: - status = isFPGAFlashStatusOk(); - break; - - case FPGA_CHECK_FIFO_COUNT: - status = isFPGAFIFOStatusOk(); - break; - default: // Do nothing break; @@ -468,58 +456,40 @@ return status; } -static BOOL isFPGAEraseFlashStatusOk( void ) +static void processFPGAFlashStatus( void ) { - U08 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; - U16 flashStatus = 0; - BOOL eraseStatus = FALSE; + U16 flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); + U16 fifoStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) ], + fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) - 1 ] ); - memcpy( &flashStatus, &fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], jobSize ); + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_NOT_READY; + fpgaFlashStatus.isFlashErased = FALSE; + fpgaFlashStatus.fifoRemainingCount = FPGA_FIFO_SIZE_BYTES - ( FPGA_FIFO_COUNT_MASK & fifoStatus ); if ( ( flashStatus & FPGA_ERASE_FIFO_CMD_OK ) == FPGA_ERASE_FIFO_CMD_OK ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; - eraseStatus = TRUE; + fpgaFlashStatus.isFlashErased = TRUE; } - return eraseStatus; -} - -static BOOL isFPGAFlashStatusOk( void ) -{ - U16 flashStatus = 0; - BOOL flashStatusOk = FALSE; - - flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], - fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); - if ( ( flashStatus & FPGA_FLASH_STATUS_OK ) == FPGA_FLASH_STATUS_OK ) { fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; - flashStatusOk = TRUE; } - return flashStatusOk; -} - -static BOOL isFPGAFIFOStatusOk( void ) -{ - U16 remFIFOCount = 0; - BOOL isStatusOk = FALSE; - - U16 word = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], - fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); - - U16 test = FPGA_FIFO_COUNT_MASK & word; - remFIFOCount = FPGA_FIFO_SIZE_BYTES - test; - - if ( remFIFOCount >= SW_UPDATE_FLASH_BUFFER_SIZE ) + if ( fpgaFlashStatus.fifoRemainingCount >= SW_UPDATE_FLASH_BUFFER_SIZE ) { - isStatusOk = TRUE; - //fpgaFlashStatus.fpgaFlashState = + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; } + else + { + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_FIFO_FULL; + } - return isStatusOk; + if ( fpgaFlashStatus.fifoRemainingCount < FPGA_FIFO_SIZE_BYTES ) // TODO remove + { + BOOL dara = FALSE; + } } static void setupDMAForReadResp( U32 bytes2Receive ) @@ -675,14 +645,22 @@ { FPGA_STATE_T state = FPGA_IDLE_STATE; - if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 ) + if ( 0 == fpgaJobsQStatus.fpgaJobsQueueCount ) { - dequeue(); - - state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); } + dequeue(); + + state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); + // TODo remove + if ( ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) && ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) ) + { + nonZeroCount[ nonzeroCounter ] = fpgaFlashStatus.fifoRemainingCount; + nonzeroCounter++; + } + if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob ) { BOOL test = FALSE; @@ -756,10 +734,13 @@ // Does the FPGA response CRC checkout? if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) ) { - if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) // TODO REMOVE + if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) { - TESTREMOVE += 1; //fpgaDataLenToWrite; - //countRemove += 1; + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY; + sendFPGAAckNackStatus( ACK ); + + TESTREMOVE += fpgaDataLenToWrite;// TODO REMOVE + countRemove += 1;// TODO REMOVE } // CRC passed @@ -795,6 +776,7 @@ // Prep DMA for sending the read cmd and receiving the response fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS; + fpgaFlashStatus.startTime = getMSTimerCount(); setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) ); @@ -823,11 +805,16 @@ memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); - state = ( TRUE == status ? FPGA_IDLE_STATE : FPGA_READ_FROM_FPGA_STATE ); // TODO have a limit + state = FPGA_IDLE_STATE; } } } + if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) ) + { + state = FPGA_IDLE_STATE; + } + resetFPGACommFlags(); // Should not be any data received at this time