Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r0595b4b31cef5980bc589ff7ce39a4e97bc81d8d -r012573b1913d1bfd2357acfadcad6bb20b295ad9 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 0595b4b31cef5980bc589ff7ce39a4e97bc81d8d) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 012573b1913d1bfd2357acfadcad6bb20b295ad9) @@ -98,7 +98,7 @@ typedef struct { U16 fpgaJobAddress; - U08 fpgaJobSize; + U16 fpgaJobSize; U08* fpgaWriteStartAddress; U08 fpgaIsJobWrite; } FPGA_JOB_SPECS_T; @@ -149,8 +149,10 @@ static U08 fpgaUpdateRegisterStatus; static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; static FPGA_FLASH_STATUS_T fpgaFlashStatus; +static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; +static U32 fpgaDataLenToWrite; -static U32 TESTTIMEREMOVE; +static U32 TESTREMOVE = 0; // TODO remove static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF }; // TODO update with the real FPGA IDs static const U16 DISABLE_UPDATE_REG_CMD = 5; // TODO what is this value? 0? @@ -169,7 +171,7 @@ { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_ERASE_FIFO_STATUS { FPGA_FLASH_STATUS_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FLASH_READY_STATUS { FPGA_FIFO_COUNT_REG_ADDR, sizeof( U16 ), 0, FALSE }, // FPGA_CHECK_FIFO_COUNT - { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaWriteCmdBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA + { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; @@ -192,6 +194,7 @@ static void resetFPGACommFlags( void ); static void enqueue( FPGA_JOBS_T job ); static void dequeue( void ); +static BOOL isQueueFull( void ); static FPGA_STATE_T handleFPGAIdleState( void ); @@ -290,28 +293,42 @@ void signalFPGAToPrepareForUpdate( void ) { - enqueue( FPGA_RESET_FLASH ); - enqueue( FPGA_ERASE_FIFO ); - enqueue( FPGA_ENABLE_FLASH ); - enqueue( FPGA_CHECK_ERASE_FIFO_STATUS ); + if ( FALSE == isQueueFull() ) + { + //enqueue( FPGA_RESET_FLASH ); + //enqueue( FPGA_ERASE_FIFO ); + enqueue( FPGA_ENABLE_FLASH ); + //enqueue( FPGA_CHECK_ERASE_FIFO_STATUS ); + } } void signalFPGAToWriteToFlash( U08* data, U32 len ) { - enqueue( FPGA_CHECK_FLASH_READY_STATUS ); - enqueue( FPGA_CHECK_FIFO_COUNT ); - enqueue( FPGA_FLASH_WRITE_DATA ); - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only - enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + if ( FALSE == isQueueFull() ) + { + memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); - memcpy( fpgaWriteCmdBuffer, data, len ); + //enqueue( FPGA_CHECK_FLASH_READY_STATUS ); + //enqueue( FPGA_CHECK_FIFO_COUNT ); + enqueue( FPGA_FLASH_WRITE_DATA ); + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only + fpgaDataLenToWrite = len; + memcpy( fpgaDataToWriteBuffer, data, len ); - fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_BUSY; + fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_BUSY; + } } +void signalFPGAToSelfConfigure( void ) +{ + if ( FALSE == isQueueFull() ) + { + enqueue( FPGA_SELF_CONFIGURE ); + } +} + // ********** private functions ********** static void initDMA( void ) @@ -490,10 +507,12 @@ U16 remFIFOCount = 0; BOOL isStatusOk = FALSE; - remFIFOCount = FPGA_FIFO_COUNT_MASK & MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], - fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); - remFIFOCount = FPGA_FIFO_SIZE_BYTES - remFIFOCount; + U16 word = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], + fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); + U16 test = FPGA_FIFO_COUNT_MASK & word; + remFIFOCount = FPGA_FIFO_SIZE_BYTES - test; + if ( remFIFOCount >= SW_UPDATE_FLASH_BUFFER_SIZE ) { isStatusOk = TRUE; @@ -640,6 +659,18 @@ _enable_IRQ(); } +static BOOL isQueueFull( void ) +{ + BOOL isFull = FALSE; + + if ( fpgaJobsQStatus.fpgaJobsQueueCount >= ( QUEUE_MAX_SIZE - 1 ) ) + { + isFull = TRUE; + } + + return isFull; +} + static FPGA_STATE_T handleFPGAIdleState( void ) { FPGA_STATE_T state = FPGA_IDLE_STATE; @@ -651,6 +682,13 @@ state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); } + // TODo remove + if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob ) + { + BOOL test = FALSE; + } + // TODo remove + return state; } @@ -659,18 +697,31 @@ FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; U16 crc = 0; U16 jobAddress = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobAddress; - U08 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U16 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + + if ( ( fpgaDataLenToWrite != SW_UPDATE_FLASH_BUFFER_SIZE ) && ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) ) + { + jobSize = (U16)fpgaDataLenToWrite; + } + + // TODO remove + if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) + { + BOOL Test = FALSE; + } + // TODO remove + U08* value2Write = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaWriteStartAddress; - U08 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; - U08 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; + U16 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; + U16 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; memcpy( &fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ], value2Write, jobSize ); // Construct bulk read command to read sensor data registers starting at address 8 fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); - fpgaWriteCmdBuffer[ 3 ] = jobSize; + fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + jobSize ); fpgaWriteCmdBuffer[ firstCRCIndex ] = GET_MSB_OF_WORD( crc ); fpgaWriteCmdBuffer[ secondCRCIndex ] = GET_LSB_OF_WORD( crc ); @@ -686,8 +737,6 @@ startDMAReceiptOfWriteResp(); startDMAWriteCmd(); - TESTTIMEREMOVE = getMSTimerCount(); - return state; } @@ -707,21 +756,22 @@ // Does the FPGA response CRC checkout? if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) ) { - if ( TRUE == didTimeout( TESTTIMEREMOVE, 3000) ) + if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) // TODO REMOVE { - // CRC passed - state = FPGA_IDLE_STATE; - memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO remove - + TESTREMOVE += 1; //fpgaDataLenToWrite; + //countRemove += 1; } + + // CRC passed + state = FPGA_IDLE_STATE; } else { // TODO error handling } } - // memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this + memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } return state;