Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -ra858229eb2ab05404dba3e29c95e2d5f7800efe6 -rfc99f47309c9d96f73a2d4696b42d6d302f334a7
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision a858229eb2ab05404dba3e29c95e2d5f7800efe6)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision fc99f47309c9d96f73a2d4696b42d6d302f334a7)
@@ -61,6 +61,8 @@
 #define FPGA_ERASE_FIFO_CMD_OK          ( 1 << 11 )
 #define FPGA_FLASH_STATUS_OK            ( 1 << 15 )
 
+#define FPGA_PRE_SELF_CONFIG_TIMEOUT_MS 10000
+
 typedef enum
 {
     FPGA_COMM_IDLE = 0,
@@ -121,8 +123,10 @@
     U16 fifoRemainingCount;
     BOOL isFlashEraseOk;
     BOOL isFlashStatusOk;
+    BOOL isFPGAFlashComplete;
     U16 flashStatusBits;
-    FPGA_FLASH_STATE_T fpgaFlashState;
+    U32 preSelfConfigureStartTimeMS;
+    FPGA_FLASH_STATE_T fpgaFlashState;  // TODO remove
     U32 startTime;
 } FPGA_FLASH_STATUS_T;
 
@@ -306,9 +310,9 @@
     return status;
 }
 
-FPGA_FLASH_STATE_T getFPGAFlashState( void )
+BOOL isFPGAFlashComplete( void )
 {
-    return fpgaFlashStatus.fpgaFlashState;
+    return fpgaFlashStatus.isFPGAFlashComplete;
 }
 
 void signalFPGAToPrepareForUpdate( void )
@@ -340,6 +344,8 @@
 {
     if ( FALSE == isQueueFull() )
     {
+        fpgaFlashStatus.preSelfConfigureStartTimeMS = getMSTimerCount();
+
         enqueue( FPGA_SELF_CONFIGURE );
     }
 }
@@ -677,12 +683,22 @@
         if ( FPGA_FLASH_WRITE_DATA == peekFromQueue() )
         {
             if ( ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) ||
-                 ( FALSE == fpgaFlashStatus.isFlashStatusOk ) || ( FALSE == fpgaFlashStatus.isFlashEraseOk ) )
+                 ( FALSE == fpgaFlashStatus.isFlashStatusOk )                         ||
+                 ( FALSE == fpgaFlashStatus.isFlashEraseOk ) )
             {
                 isDequeueAllowed = FALSE;
             }
         }
 
+        if ( FPGA_SELF_CONFIGURE == peekFromQueue() )
+        {
+            if ( ( FALSE == didTimeout( fpgaFlashStatus.preSelfConfigureStartTimeMS, FPGA_PRE_SELF_CONFIG_TIMEOUT_MS ) ) ||
+                 ( FALSE == fpgaFlashStatus.isFlashStatusOk ) )
+            {
+                isDequeueAllowed = FALSE;
+            }
+        }
+
         if ( TRUE == isDequeueAllowed )
         {
             dequeue();
@@ -693,14 +709,6 @@
 
     requestFlashRegistersStatus();
 
-    // TODo remove
-    tempACkStatus = NACK;
-    if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob )
-    {
-        BOOL test = FALSE;
-    }
-    // TODo remove
-
     return state;
 }
 
@@ -716,12 +724,13 @@
         jobSize = (U16)fpgaDataLenToWrite;
     }
 
-    // TODO remove
-    if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob )
+    if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob )
     {
-        BOOL Test = FALSE;
+        // Once self configure is sent the FPGA will be unresponsive so there will be no ack back
+        // Signal FPGA is completed
+        state                               = FPGA_IDLE_STATE;
+        fpgaFlashStatus.isFPGAFlashComplete = TRUE;
     }
-    // TODO remove
 
     U08* value2Write   = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaWriteStartAddress;
     U16 firstCRCIndex  = FPGA_WRITE_CMD_HDR_LEN + jobSize;