Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rb1729daefa724d159fa59448cbc87dea54e982d7 -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision b1729daefa724d159fa59448cbc87dea54e982d7) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -56,15 +56,16 @@ #define FPGA_FLASH_CONTROL_REG_ADDR 0x120E ///< FPGA flash control register address. #define FPGA_MULTI_BOOT_STATUS_ADDR 0x1200 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x1209 ///< FPGA ICAP 2 command register address. +#define FPGA_FLASH_DATA_REG_ADDR 0x1400 ///< FPGA flash data register address. #else #define FPGA_FLASH_CONTROL_REG_ADDR 0x090E ///< FPGA flash control register address. #define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. +#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. #endif #define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe #define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe -#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe #define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) ///< FPGA update register address. #define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA update request index. // TODO Get this value from Noe, make sure the index is the same in all of the stacks @@ -96,7 +97,7 @@ typedef enum { FPGA_READ_HEADER = 0, ///< FPGA read header. - FPGA_READ_UPDATE_REG, ///< FPGA read update request register. + FPGA_READ_UPDATE_REG, // TODO remove? ///< FPGA read update request register. FPGA_WRITE_UPDATE_REG, ///< FPGA write to update request register. FPGA_RESET_FLASH, ///< FPGA reset flash. FPGA_ERASE_FIFO, ///< FPGA erase FIFO. @@ -140,6 +141,18 @@ FPGA_COMM_STATE_T fpgaCommWrite; ///< FPGA DMA write command state. } FPGA_JOBS_Q_STATUS_T; +/// FPGA read registers status structure +typedef struct +{ + U16 flashStatus; ///< FPGA flash status. + U16 fifoCount; ///< FPGA FIFO count. + U32 icape2DataIn; ///< FPGA ICAPE2 datain. + U08 icape2Address; ///< FPGA ICAPE2 address. + U08 icape2Cmd; ///< FPGA ICAPE2 command. + U32 icape2DataOut; ///< FPGA ICAPE2 dataout. + U08 flashIntCtrlReg; ///< FPGA flash interface control register. +} FPGA_READ_REGS_T; + /// FPGA flash status structure typedef struct { @@ -182,6 +195,7 @@ static U08 fpgaUpdateRegisterStatus; ///< FPGA update register status. static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; ///< FPGA jobs queue status. static FPGA_FLASH_STATUS_T fpgaFlashStatus; ///< FPGA flash status. +static FPGA_READ_REGS_T fpgaReadRegsStatus; ///< FGPA read registers status. static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; ///< FPGA data to write to FPGA flash buffer. static U32 fpgaDataLenToWrite; ///< FPGA data length to write to FPGA. @@ -190,9 +204,9 @@ static U08 tempACkStatus = 0; // TODO remove /// FPGA stack ID for TD, DD -static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs +static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs // TODO remove // TODO what is this value? 0? -static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. +static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. // TODO remove static const U08 FPGA_RESET_FLASH_CMD = 0x01; ///< FPGA reset flash command. static const U08 FPGA_ERASE_FIFO_CMD = 0x08; ///< FPGA erase FIFO command. static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; ///< FPGA enable flash command. @@ -201,12 +215,14 @@ /// FPGA jobs specifications. static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER - { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // FPGA_READ_UPDATE_REG + { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // TODO remove // FPGA_READ_UPDATE_REG { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), (U08*)&DISABLE_UPDATE_REG_CMD, TRUE }, // FPGA_WRITE_UPDATE_REG + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH - { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( U32 ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS + { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( FPGA_READ_REGS_T ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; @@ -250,15 +266,21 @@ *************************************************************************/ void initFPGA( void ) { - memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); + memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); memset( &fpgaJobsQStatus, 0x0, sizeof( FPGA_JOBS_Q_STATUS_T ) ); memset( &fpgaFlashStatus, 0x0, sizeof( FPGA_FLASH_STATUS_T ) ); + // initialize fpga comm buffers + memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN ); + memset( &fpgaReadCmdBuffer, 0, FPGA_READ_CMD_BUFFER_LEN ); + memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); + memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); + initDMA(); consumeUnexpectedData(); enqueue( FPGA_READ_HEADER ); - enqueue( FPGA_READ_UPDATE_REG ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); fpgaState = FPGA_IDLE_STATE; fpgaUpdateRegisterStatus = 0; @@ -273,22 +295,17 @@ *************************************************************************/ void execFPGA( void ) { - if ( TRUE == fpgaFlashStatus.hasUpdateRegsBeenRqstd ) - { - processFPGAFlashRegistersRead(); - } - // TODO test code remove - //U08 data[8]; - //data[0] = getTempRemoveMSGID(); - //data[1] = (U08)fpgaState; - //data[2] = GET_LSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - //data[3] = GET_MSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - //data[4] = GET_LSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - //data[5] = GET_MSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - //data[6] = tempACkStatus; - //data[7] = (U08)fpgaFlashStatus.isFlashStatusOk; - //broadcastDataTestRemove(data); + U08 data[8]; + data[0] = GET_LSB_OF_WORD( getCurrentUpdateMessageID() ); + data[1] = GET_MSB_OF_WORD( getCurrentUpdateMessageID() ); + data[2] = GET_LSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); + data[3] = GET_MSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); + data[4] = GET_LSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); + data[5] = GET_MSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); + data[6] = fpgaJobsQStatus.fpgaCurrentJob; + data[7] = (U08)fpgaState; + broadcastDataTestRemove(data); // TODO test code remove switch( fpgaState ) @@ -333,7 +350,6 @@ if ( FPGA_COMM_WRITE_IN_PROGRESS == fpgaJobsQStatus.fpgaCommWrite ) { fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_WRITE_RESP_RECEIVED; - requestFlashRegistersStatus(); } else if ( FPGA_COMM_READ_IN_PROGRESS == fpgaJobsQStatus.fpgaCommRead ) { @@ -585,8 +601,8 @@ fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); #if BL_STACK_ID == 1 - fpgaReadCmdBuffer[ 3 ] = jobSize; - fpgaReadCmdBuffer[ 4 ] = 0; + fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize ); + fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize ); #else fpgaReadCmdBuffer[ 3 ] = jobSize; #endif @@ -933,7 +949,7 @@ } } - requestFlashRegistersStatus(); + //requestFlashRegistersStatus(); // TODO remove return state; } @@ -979,8 +995,8 @@ fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); #if BL_STACK_ID == 1 - fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; - fpgaWriteCmdBuffer[ 4 ] = 0; + fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); + fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); #else fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; #endif @@ -1047,7 +1063,7 @@ memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } - requestFlashRegistersStatus(); + //requestFlashRegistersStatus(); return state; } @@ -1115,7 +1131,8 @@ { if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) { - U32 rspSize = FPGA_READ_RSP_HDR_LEN + JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U16 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U32 rspSize = FPGA_READ_RSP_HDR_LEN + jobSize; U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); @@ -1125,27 +1142,33 @@ switch( fpgaJobsQStatus.fpgaCurrentJob ) { case FPGA_READ_HEADER: - memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); + memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], jobSize ); break; case FPGA_READ_UPDATE_REG: fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; break; + case FPGA_READ_MULTI_BOOT_STATUS: + memcpy( &fpgaReadRegsStatus, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], jobSize ); + break; + default: // Do nothing break; } memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); state = FPGA_IDLE_STATE; } } } if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) ) { + // TODO a request multiboot here state = FPGA_IDLE_STATE; }