Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rb8160225a28a2ba4d6dff4d0433e55465c737a14 -rc74c1d99a011dd0fb7f98f183faecda675221fce --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision b8160225a28a2ba4d6dff4d0433e55465c737a14) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision c74c1d99a011dd0fb7f98f183faecda675221fce) @@ -1,9 +1,3 @@ -/* - * FPGA.c - * - * Created on: Aug 15, 2024 - * Author: fw - */ #include // For memcpy and memset @@ -17,129 +11,144 @@ #include "SystemComm.h" #include "Utilities.h" -#define QUEUE_MAX_SIZE 20 ///< Max queue size. -#define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. -#define FPGA_MAX_READ_SIZE ( FPGA_PAGE_SIZE - 1 ) -#define FPGA_WRITE_CMD_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA write command buffer byte length. -#define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. -#define FPGA_WRITE_RSP_BUFFER_LEN 8 ///< FPGA write command response buffer byte length. -#define FPGA_READ_RSP_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA read command response buffer byte length. +/** + * @addtogroup FPGA + * @{ + */ -#define SCI2_RECEIVE_DMA_REQUEST 28 ///< Serial port 2 receive DMA request line. -#define SCI2_TRANSMIT_DMA_REQUEST 29 ///< Serial port 2 transmit DMA request line. +// ********** private definitions ********** -#define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. -#define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. -#define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. +#define QUEUE_MAX_SIZE 20 ///< Max queue size. +#define FPGA_PAGE_SIZE 256 ///< FPGA register pages are 256 bytes. +#define FPGA_MAX_READ_SIZE ( FPGA_PAGE_SIZE - 1 ) ///< FGPA max read size. +#define FPGA_WRITE_CMD_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA write command buffer byte length. +#define FPGA_READ_CMD_BUFFER_LEN 8 ///< FPGA read command buffer byte length. +#define FPGA_WRITE_RSP_BUFFER_LEN 8 ///< FPGA write command response buffer byte length. +#define FPGA_READ_RSP_BUFFER_LEN ( FPGA_PAGE_SIZE + 8 ) ///< FPGA read command response buffer byte length. -#define FPGA_WRITE_CMD_CODE 0x55 ///< FPGA write command code. -#define FPGA_WRITE_CMD_ACK 0xA5 ///< FPGA write command ACK code. -#define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. -#define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. -#define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. -#define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. -#define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO does this vary? +#define SCI2_RECEIVE_DMA_REQUEST 28 ///< Serial port 2 receive DMA request line. +#define SCI2_TRANSMIT_DMA_REQUEST 29 ///< Serial port 2 transmit DMA request line. + +#define FPGA_CRC_LEN 2 ///< FPGA CRC byte length. +#define FPGA_WRITE_CMD_HDR_LEN 4 ///< FPGA write command header byte length. +#define FPGA_WRITE_RSP_HDR_LEN 3 ///< FPGA write command response header byte length. + +#define FPGA_WRITE_CMD_CODE 0x55 ///< FPGA write command code. +#define FPGA_WRITE_CMD_ACK 0xA5 ///< FPGA write command ACK code. +#define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. +#define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. +#define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. +#define FPGA_BULK_READ_START_ADDR 0x0100 ///< Start address for FPGA continuous priority reads. +#define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO does this vary? #define FPGA_FLASH_CONTROL_REG_ADDR 0x090E -#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe -#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe -#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe -#define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. -#define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. +#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe +#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe +#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe +#define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. +#define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. -#define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) -#define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. -#define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. -#define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) // TODO Get this value from Noe, make sure the index is the same in all of the stacks -#define FPGA_FLASH_STATUS_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) -#define FPGA_FIFO_COUNT_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) +#define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) ///< FPGA update register address. +#define FPGA_READ_CMD_HDR_LEN 4 ///< FPGA read command header byte length. +#define FPGA_READ_RSP_HDR_LEN 3 ///< FPGA read command response header byte length. +#define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA update request index. // TODO Get this value from Noe, make sure the index is the same in all of the stacks +#define FPGA_FLASH_STATUS_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA flash status index. +#define FPGA_FIFO_COUNT_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA FIFO count index. -#define UPDATE_REQUESTED_VALUE 1 +#define UPDATE_REQUESTED_VALUE 1 ///< The value that indicates and update has been requested. -#define FPGA_FIFO_SIZE_BYTES 1024 -#define FPGA_FIFO_COUNT_MASK 0x03FF +#define FPGA_FIFO_SIZE_BYTES 1024 ///< FPGA FIFO size in bytes. +#define FPGA_FIFO_COUNT_MASK 0x03FF ///< FPGA FIFO count in FIFO mask. -#define FPGA_ERASE_FIFO_CMD_OK ( 1 << 11 ) -#define FPGA_FLASH_STATUS_OK ( 1 << 15 ) +#define FPGA_ERASE_FIFO_CMD_OK ( 1 << 11 ) ///< FPGA erase FIFO command status ok value. +#define FPGA_FLASH_STATUS_OK ( 1 << 15 ) ///< FPGA flash status status ok value. -#define FPGA_PRE_SELF_CONFIG_TIMEOUT_MS 10000 +#define FPGA_PRE_SELF_CONFIG_TIMEOUT_MS 10000 ///< FPGA pre self configure timeout in milliseconds. +/// FPGA communication status enumeration typedef enum { - FPGA_COMM_IDLE = 0, - FPGA_COMM_READ_IN_PROGRESS, - FPGA_COMM_READ_RESP_RECEIVED, - FPGA_COMM_WRITE_IN_PROGRESS, - FPGA_COMM_WRITE_RESP_RECEIVED, - NUM_OF_FPGA_COMM_STATUS + FPGA_COMM_IDLE = 0, ///< FPGA communication idle. + FPGA_COMM_READ_IN_PROGRESS, ///< FPGA communication read in progress. + FPGA_COMM_READ_RESP_RECEIVED, ///< FPGA communication read response received. + FPGA_COMM_WRITE_IN_PROGRESS, ///< FPGA communication write in progress. + FPGA_COMM_WRITE_RESP_RECEIVED, ///< FPGA communication write response received. + NUM_OF_FPGA_COMM_STATUS ///< Number of FPGA communication status. } FPGA_COMM_STATE_T; +/// FPGA queue jobs enumeration typedef enum { - FPGA_READ_HEADER = 0, - FPGA_READ_UPDATE_REG, - FPGA_WRITE_UPDATE_REG, - FPGA_RESET_FLASH, - FPGA_ERASE_FIFO, - FPGA_ENABLE_FLASH, - FPGA_READ_MULTI_BOOT_STATUS, - FPGA_FLASH_WRITE_DATA, - FPGA_SELF_CONFIGURE, - NUM_OF_FPGA_JOBS, + FPGA_READ_HEADER = 0, ///< FPGA read header. + FPGA_READ_UPDATE_REG, ///< FPGA read update request register. + FPGA_WRITE_UPDATE_REG, ///< FPGA write to update request register. + FPGA_RESET_FLASH, ///< FPGA reset flash. + FPGA_ERASE_FIFO, ///< FPGA erase FIFO. + FPGA_ENABLE_FLASH, ///< FPGA enable flash. + FPGA_READ_MULTI_BOOT_STATUS, ///< FPGA read multi-boot status. + FPGA_FLASH_WRITE_DATA, ///< FPGA write flash data. + FPGA_SELF_CONFIGURE, ///< FPGA self configure. + NUM_OF_FPGA_JOBS, ///< Number of the FPGA jobs. } FPGA_JOBS_T; +/// FPGA state machine states enumeration typedef enum { - FPGA_IDLE_STATE = 0, - FPGA_WRITE_TO_FPGA_STATE, - FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE, - FPGA_READ_FROM_FPGA_STATE, - FPGA_RCV_READ_RESP_FROM_FPGA_STATE, - NUM_OF_FPGA_STATES + FPGA_IDLE_STATE = 0, ///< FPGA idle state. + FPGA_WRITE_TO_FPGA_STATE, ///< FPGA write to FPGA state. + FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE, ///< FPGA receive write response from FPGA state. + FPGA_READ_FROM_FPGA_STATE, ///< FPGA read from FPGA state. + FPGA_RCV_READ_RESP_FROM_FPGA_STATE, ///< FPGA received read response from FPGA state. + NUM_OF_FPGA_STATES ///< Number of FPGA states. } FPGA_STATE_T; #pragma pack(push,1) +/// FPGA queue job specification structure typedef struct { - U16 fpgaJobAddress; - U16 fpgaJobSize; - U08* fpgaWriteStartAddress; - U08 fpgaIsJobWrite; + U16 fpgaJobAddress; ///< FPGA job address. + U16 fpgaJobSize; ///< FPGA job size. + U08* fpgaWriteStartAddress; ///< FPGA write buffer start address. + U08 fpgaIsJobWrite; ///< FPGA boolean flag to indicate this is a write job or not. } FPGA_JOB_SPECS_T; +/// FPGA jobs queue status structure typedef struct { - U08 fpgaJobsQueue[ QUEUE_MAX_SIZE ]; - U08 fpgaJobRearIndex; - U08 fpgaJobFrontIndex; - U08 fpgaJobsQueueCount; - U08 fpgaCurrentJob; - FPGA_COMM_STATE_T fpgaCommRead; - FPGA_COMM_STATE_T fpgaCommWrite; + U08 fpgaJobsQueue[ QUEUE_MAX_SIZE ]; ///< FPGA jobs queue. + U08 fpgaJobRearIndex; ///< FPGA job queue rear index. + U08 fpgaJobFrontIndex; ///< FPGA job queue front index. + U08 fpgaJobsQueueCount; ///< FPGA job queue count. + U08 fpgaCurrentJob; ///< FPGA queue current job. + FPGA_COMM_STATE_T fpgaCommRead; ///< FPGA DMA read command state. + FPGA_COMM_STATE_T fpgaCommWrite; ///< FPGA DMA write command state. } FPGA_JOBS_Q_STATUS_T; +/// FPGA flash status structure typedef struct { - BOOL hasUpdateRegsBeenRqstd; - U16 fifoRemainingCount; - BOOL isFlashEraseOk; - BOOL isFlashStatusOk; - BOOL isFPGAFlashComplete; - U16 flashStatusBits; - U32 preSelfConfigureStartTimeMS; - U32 startTime; + BOOL hasUpdateRegsBeenRqstd; ///< Flag to indicate whether update registers request has been requested. + U16 fifoRemainingCount; ///< FIFO empty space remaining count. + BOOL isFIFOEraseOk; ///< Flag to indicate whether FIFO has been erased or not. + BOOL isFlashStatusOk; ///< Flag to indicate whether flash status is okay or not. + BOOL isFPGAFlashComplete; ///< Flag to indicate whether flash update has been completed. + U16 flashStatusBits; ///< Flash status. + U32 preSelfConfigureStartTimeMS; ///< Pre self configure start time in milliseconds. + U32 startTime; ///< Start time in milliseconds. } FPGA_FLASH_STATUS_T; /// Record structure for FPGA header read. typedef struct { - U08 fpgaId; ///< Reg 0. FPGA ID code. Checked against expected value at power up to verify basic FPGA communication and operation. - U08 fpgaRev; ///< Reg 1. FPGA revision (minor) being reported. - U08 fpgaRevMajor; ///< Reg 2. FPGA revision (major) being reported. - U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported. - U16 fpgaStatus; ///< Reg 4. FPGA status register. + U08 fpgaId; ///< Reg 0. FPGA ID code. Checked against expected value at power up to verify basic FPGA communication and operation. + U08 fpgaRev; ///< Reg 1. FPGA revision (minor) being reported. + U08 fpgaRevMajor; ///< Reg 2. FPGA revision (major) being reported. + U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported. + U16 fpgaStatus; ///< Reg 4. FPGA status register. } FPGA_HEADER_T; // Read only on FPGA #pragma pack(pop) +// ********** private data ********** + // FPGA comm buffers static U08 fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_BUFFER_LEN ]; ///< FPGA write command buffer. Holds the next FPGA write command to be transmitted. static U08 fpgaReadCmdBuffer[ FPGA_READ_CMD_BUFFER_LEN ]; ///< FPGA read command buffer. Holds the next FPGA read command to be transmitted. @@ -152,25 +161,27 @@ static g_dmaCTRL fpgaDMAReadControlRecord; ///< DMA record for controlling a DMA read command transmission from buffer. static g_dmaCTRL fpgaDMAReadRespControlRecord; ///< DMA record for controlling a DMA read command reception to buffer. -static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data. -static FPGA_STATE_T fpgaState; -static U08 fpgaUpdateRegisterStatus; -static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; -static FPGA_FLASH_STATUS_T fpgaFlashStatus; -static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; -static U32 fpgaDataLenToWrite; +static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data. +static FPGA_STATE_T fpgaState; ///< FPGA current state. +static U08 fpgaUpdateRegisterStatus; ///< FPGA update register status. +static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; ///< FPGA jobs queue status. +static FPGA_FLASH_STATUS_T fpgaFlashStatus; ///< FPGA flash status. +static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; ///< FPGA data to write to FPGA flash buffer. +static U32 fpgaDataLenToWrite; ///< FPGA data length to write to FPGA. static U32 TESTREMOVE = 0; // TODO remove static U32 countRemove = 0; // TODO remove -static U08 tempACkStatus = 0; +static U08 tempACkStatus = 0; // TODO remove +/// FPGA stack ID for TD, DD, RO. static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF }; // TODO update with the real FPGA IDs -static const U16 DISABLE_UPDATE_REG_CMD = 5; // TODO what is this value? 0? -static const U08 FPGA_RESET_FLASH_CMD = 0x01; -static const U08 FPGA_ERASE_FIFO_CMD = 0x08; -static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; -static const U08 FPGA_SELF_CONFIG_CMD = 0x03; +static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. // TODO what is this value? 0? +static const U08 FPGA_RESET_FLASH_CMD = 0x01; ///< FPGA reset flash command. +static const U08 FPGA_ERASE_FIFO_CMD = 0x08; ///< FPGA erase FIFO command. +static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; ///< FPGA enable flash command. +static const U08 FPGA_SELF_CONFIG_CMD = 0x03; ///< FPGA self configure command. +/// FPGA jobs specifications. static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // FPGA_READ_UPDATE_REG @@ -183,6 +194,8 @@ { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; +// ********** private function prototypes ********** + static void initDMA( void ); static void consumeUnexpectedData( void ); static void requestFlashRegistersStatus( void ); @@ -211,6 +224,13 @@ static FPGA_STATE_T handleFPGAReadFromFPGAState( void ); static FPGA_STATE_T handleFPGAReceiveReadRespFromFPGAState( void ); +/*********************************************************************//** + * @brief + * The initFPGA function initializes the FPGA unit. + * @details \b Inputs: none + * @details \b Outputs: FPGA unit initialized. + * @return none + *************************************************************************/ void initFPGA( void ) { memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); @@ -227,6 +247,13 @@ fpgaUpdateRegisterStatus = 0; } +/*********************************************************************//** + * @brief + * The execFPGA function the FPGA state machine. + * @details \b Inputs: fpgaState + * @details \b Outputs: fpgaState + * @return none + *************************************************************************/ void execFPGA( void ) { if ( TRUE == fpgaFlashStatus.hasUpdateRegsBeenRqstd ) @@ -275,6 +302,15 @@ } } +/*********************************************************************//** + * @brief + * The signalFPGAReceiptCompleted function increments a counter to indicate + * that another DMA receipt from the FPGA has completed and sets comm flags + * indicating pending response from FPGA is completed. + * @details \b Inputs: fpgaJobsQStatus + * @details \b Outputs: fpgaJobsQStatus + * @return none + *************************************************************************/ void signalFPGAReceiptCompleted( void ) { if ( FPGA_COMM_WRITE_IN_PROGRESS == fpgaJobsQStatus.fpgaCommWrite ) @@ -288,6 +324,14 @@ } } +/*********************************************************************//** + * @brief + * The hasUpdateBeenRequested function checks whether an update has been + * requested through the FPGA read registers. + * @details \b Inputs: fpgaState, fpgaUpdateRegisterStatus + * @details \b Outputs: fpgaUpdateRegisterStatus + * @return TRUE if an update has been requested otherwise, FALSE + *************************************************************************/ BOOL hasUpdateBeenRequested( void ) { BOOL status = FALSE; @@ -302,18 +346,41 @@ return status; } +/*********************************************************************//** + * @brief + * The isFPGAIDValid function checks whether the FPGA header is valid. + * @details \b Inputs: fpgaHeader + * @details \b Outputs: none + * @return TRUE if the FPGA header is valid otherwise, FALSE + *************************************************************************/ BOOL isFPGAIDValid( void ) { BOOL status = ( STACK_FPGA_ID[ BL_STACK_ID ] == fpgaHeader.fpgaId ? TRUE : FALSE ); return status; } +/*********************************************************************//** + * @brief + * The isFPGAFlashComplete function returns the status of FPGA flash. So + * TRUE if the flash is complete, otherwise, FALSE. + * @details \b Inputs: fpgaFlashStatus + * @details \b Outputs: none + * @return the status of the FPGA flash + *************************************************************************/ BOOL isFPGAFlashComplete( void ) { return fpgaFlashStatus.isFPGAFlashComplete; } +/*********************************************************************//** + * @brief + * The signalFPGAToPrepareForUpdate function enqueues the FPGA update + * initialization jobs if the queue is not full. + * @details \b Inputs: none + * @details \b Outputs: none + * @return none + *************************************************************************/ void signalFPGAToPrepareForUpdate( void ) { if ( FALSE == isQueueFull() ) @@ -324,6 +391,14 @@ } } +/*********************************************************************//** + * @brief + * The signalFPGAToWriteToFlash function enqueues the FPGA write to flash + * job if the queue is not full. + * @details \b Inputs: none + * @details \b Outputs: fpgaDataLenToWrite, fpgaDataToWriteBuffer + * @return none + *************************************************************************/ void signalFPGAToWriteToFlash( U08* data, U32 len ) { if ( FALSE == isQueueFull() ) @@ -337,6 +412,14 @@ } } +/*********************************************************************//** + * @brief + * The signalFPGAToSelfConfigure function enqueues the FPGA self configure + * job if the queue is not full. + * @details \b Inputs: none + * @details \b Outputs: fpgaFlashStatus + * @return none + *************************************************************************/ void signalFPGAToSelfConfigure( void ) { if ( FALSE == isQueueFull() ) @@ -349,6 +432,13 @@ // ********** private functions ********** +/*********************************************************************//** + * @brief + * The initDMA function initializes the DMA communication. + * @details \b Inputs: none + * @details \b Outputs: FPGA DMA unit initialized. + * @return none + *************************************************************************/ static void initDMA( void ) { // Enable interrupt notifications for FPGA serial port @@ -439,6 +529,14 @@ fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // Not used } +/*********************************************************************//** + * @brief + * The consumeUnexpectedData function checks to see if a byte is sitting in + * the SCI2 received data register and consumes the byte if found. + * @details \b Inputs: SCI FLR register + * @details \b Outputs: SCI errors cleared, unexpected byte consumed + * @return none + *************************************************************************/ static void consumeUnexpectedData( void ) { // Clear any errors @@ -451,6 +549,14 @@ } } +/*********************************************************************//** + * @brief + * The requestFlashRegistersStatus function requests the FPGA flash readings + * status. + * @details \b Inputs: none + * @details \b Outputs: fpgaReadCmdBuffer[], fpgaJobsQStatus, fpgaFlashStatus + * @return none + *************************************************************************/ static void requestFlashRegistersStatus( void ) { U16 jobAddress = JOBS_SPECS[ FPGA_READ_MULTI_BOOT_STATUS ].fpgaJobAddress; @@ -476,6 +582,13 @@ startDMAReadCmd(); } +/*********************************************************************//** + * @brief + * The processFPGAFlashRegistersRead function processes the read flash readings. + * @details \b Inputs: fpgaReadResponseBuffer[] + * @details \b Outputs: fpgaFlashStatus + * @return none + *************************************************************************/ static void processFPGAFlashRegistersRead( void ) { if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) @@ -498,7 +611,7 @@ if ( ( flashStatus & FPGA_ERASE_FIFO_CMD_OK ) == FPGA_ERASE_FIFO_CMD_OK ) { - fpgaFlashStatus.isFlashEraseOk = TRUE; + fpgaFlashStatus.isFIFOEraseOk = TRUE; } if ( ( flashStatus & FPGA_FLASH_STATUS_OK ) == FPGA_FLASH_STATUS_OK ) @@ -509,6 +622,16 @@ } } +/*********************************************************************//** + * @brief + * The setupDMAForReadResp function sets the expected byte count for the + * next DMA read command response from the FPGA. + * @details \b Inputs: none + * @details \b Outputs: fpgaDMAReadRespControlRecord + * @param bytes2Receive number of expected bytes to be transmitted via + * DMA from the FPGA + * @return none + *************************************************************************/ static void setupDMAForReadResp( U32 bytes2Receive ) { // Verify # of bytes does not exceed buffer length @@ -518,6 +641,15 @@ } } +/*********************************************************************//** + * @brief + * The setupDMAForReadCmd function sets the byte count for the next DMA + * read command to the FPGA. + * @details \b Inputs: none + * @details \b Outputs: fpgaDMAReadControlRecord + * @param bytes2Transmit number of bytes to be transmitted via DMA to the FPGA + * @return none + *************************************************************************/ static void setupDMAForReadCmd( U32 bytes2Transmit ) { // Verify # of bytes does not exceed buffer length @@ -527,13 +659,30 @@ } } +/*********************************************************************//** + * @brief + * The startDMAReceiptOfReadResp function initiates readiness of the DMA + * receiver for the next DMA read command response from the FPGA. + * @details \b Inputs: fpgaDMAReadRespControlRecord + * @details \b Outputs: DMA read command response is ready to be received + * from the FPGA + * @return none + *************************************************************************/ static void startDMAReceiptOfReadResp( void ) { dmaSetCtrlPacket( DMA_CH0, fpgaDMAReadRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); setSCI2DMAReceiveInterrupt(); } +/*********************************************************************//** + * @brief + * The startDMAReadCmd function initiates the DMA transmit for the next + * DMA read command to the FPGA. + * @details \b Inputs: fpgaDMAReadControlRecord + * @details \b Outputs: DMA read command to FPGA is initiated + * @return none + *************************************************************************/ static void startDMAReadCmd( void ) { dmaSetCtrlPacket( DMA_CH2, fpgaDMAReadControlRecord ); @@ -607,13 +756,27 @@ setSCI2DMAReceiveInterrupt(); } - +/*********************************************************************//** + * @brief + * The resetFPGACommFlags function resets the various fpga comm flags and + * counters. + * @details \b Inputs: none + * @details \b Outputs: fpgaJobsQStatus + * @return none + *************************************************************************/ static void resetFPGACommFlags( void ) { fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_IDLE; fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_IDLE; } +/*********************************************************************//** + * @brief + * The enqueue function enqueues a new job into the queue. + * @details \b Inputs: none + * @details \b Outputs: fpgaJobsQStatus + * @return none + *************************************************************************/ static void enqueue( FPGA_JOBS_T job ) { U08 currentRearIndex = fpgaJobsQStatus.fpgaJobRearIndex; @@ -624,6 +787,14 @@ fpgaJobsQStatus.fpgaJobRearIndex = INC_WRAP( currentRearIndex, 0, QUEUE_MAX_SIZE - 1 ); } +/*********************************************************************//** + * @brief + * The enqueue function dequeues a job from the queue. This function is thread + * safe. Prior to dequeuing a job, the IRQ interrupt is stopped. + * @details \b Inputs: fpgaJobsQStatus + * @details \b Outputs: fpgaJobsQStatus + * @return none + *************************************************************************/ static void dequeue( void ) { U08 tempIndex; @@ -646,6 +817,15 @@ _enable_IRQ(); } +/*********************************************************************//** + * @brief + * The peekFromQueue function just reports what is the next job in the queue. + * This function does not do the actual dequeue. This function is thread + * safe. Prior to peeking into the next job, the IRQ interrupt is stopped. + * @details \b Inputs: fpgaJobsQStatus + * @details \b Outputs: none + * @return the next job that is in the queue + *************************************************************************/ static FPGA_JOBS_T peekFromQueue( void ) { _disable_IRQ(); @@ -656,6 +836,13 @@ return nextJob; } +/*********************************************************************//** + * @brief + * The isQueueFull function checks whether the queue is full or not. + * @details \b Inputs: fpgaJobsQStatus + * @details \b Outputs: none + * @return TRUE if the queue is full otherwise, FALSE + *************************************************************************/ static BOOL isQueueFull( void ) { BOOL isFull = FALSE; @@ -668,6 +855,15 @@ return isFull; } +/*********************************************************************//** + * @brief + * The handleFPGAIdleState function handles the FPGA idle state. This state + * checks whether there are any jobs in the queue and processes them. This + * state also requests the flash update registers. + * @details \b Inputs: fpgaJobsQStatus, fpgaFlashStatus + * @details \b Outputs: none + * @return next state of the FPGA state machine + *************************************************************************/ static FPGA_STATE_T handleFPGAIdleState( void ) { FPGA_STATE_T state = FPGA_IDLE_STATE; @@ -678,16 +874,24 @@ if ( FPGA_FLASH_WRITE_DATA == peekFromQueue() ) { + // Check if the next job in the queue is a flash write. + // If there is a flash write, only dequeue it if: + // 1. There are at least 256 bytes available in the FIFO + // 2. The flash status is okay + // 3. The FIFO erase is okay if ( ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) || ( FALSE == fpgaFlashStatus.isFlashStatusOk ) || - ( FALSE == fpgaFlashStatus.isFlashEraseOk ) ) + ( FALSE == fpgaFlashStatus.isFIFOEraseOk ) ) { isDequeueAllowed = FALSE; } } if ( FPGA_SELF_CONFIGURE == peekFromQueue() ) { + // Check if the next job in the queue is the self configure. Then make sure: + // 1. The delay has timed out + // 2. The flash status is okay if ( ( FALSE == didTimeout( fpgaFlashStatus.preSelfConfigureStartTimeMS, FPGA_PRE_SELF_CONFIG_TIMEOUT_MS ) ) || ( FALSE == fpgaFlashStatus.isFlashStatusOk ) ) { @@ -698,7 +902,7 @@ if ( TRUE == isDequeueAllowed ) { dequeue(); - + // After dequeue based on the job specs transition to either write or read states state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE ); } } @@ -708,6 +912,15 @@ return state; } +/*********************************************************************//** + * @brief + * The handleFPGAWriteToFPGAState function handles the FPGA write to FPGA + * state. This state prepares the buffer to write to FPGA and sets the DMA + * to write to the FPGA. + * @details \b Inputs: fpgaJobsQStatus, fpgaDataLenToWrite + * @details \b Outputs: fpgaFlashStatus, fpgaWriteCmdBuffer[] + * @return next state of the FPGA state machine + *************************************************************************/ static FPGA_STATE_T handleFPGAWriteToFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; @@ -717,6 +930,7 @@ if ( ( fpgaDataLenToWrite != SW_UPDATE_FLASH_BUFFER_SIZE ) && ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) ) { + // Set the write length from the buffer length provided jobSize = (U16)fpgaDataLenToWrite; } @@ -757,6 +971,14 @@ return state; } +/*********************************************************************//** + * @brief + * The handleFPGAReceiveWriteRespFromFPGAState function handles the FPGA + * receive write to FPGA response. + * @details \b Inputs: fpgaJobsQStatus, fpgaWriteResponseBuffer[] + * @details \b Outputs: fpgaWriteResponseBuffer[] + * @return next state of the FPGA state machine + *************************************************************************/ static FPGA_STATE_T handleFPGAReceiveWriteRespFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_WRITE_RESP_FROM_FPGA_STATE; @@ -776,7 +998,7 @@ if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) { sendFPGAAckNackStatus( ACK ); - tempACkStatus = ACK; + tempACkStatus = ACK; // TODO remove TESTREMOVE += fpgaDataLenToWrite;// TODO REMOVE countRemove += 1;// TODO REMOVE @@ -799,6 +1021,13 @@ return state; } +/*********************************************************************//** + * @brief + * The handleFPGAReadFromFPGAState function handles the FPGA read from FPGA. + * @details \b Inputs: none + * @details \b Outputs: fpgaReadCmdBuffer[], fpgaJobsQStatus, fpgaFlashStatus + * @return next state of the FPGA state machine + *************************************************************************/ static FPGA_STATE_T handleFPGAReadFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_READ_RESP_FROM_FPGA_STATE; @@ -827,6 +1056,15 @@ return state; } +/*********************************************************************//** + * @brief + * The handleFPGAReceiveReadRespFromFPGAState function handles the FPGA + * read response from FPGA. + * @details \b Inputs: fpgaJobsQStatus, fpgaReadResponseBuffer[] + * @details \b Outputs: fpgaReadResponseBuffer[], fpgaHeader, + * fpgaUpdateRegisterStatus + * @return next state of the FPGA state machine + *************************************************************************/ static FPGA_STATE_T handleFPGAReceiveReadRespFromFPGAState( void ) { FPGA_STATE_T state = FPGA_RCV_READ_RESP_FROM_FPGA_STATE; @@ -877,3 +1115,5 @@ return state; } +/**@}*/ +