Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -rfc9a9244cf4288ff0623c3e02455ac565bf60cdd -rb1729daefa724d159fa59448cbc87dea54e982d7
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision fc9a9244cf4288ff0623c3e02455ac565bf60cdd)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision b1729daefa724d159fa59448cbc87dea54e982d7)
@@ -19,7 +19,19 @@
 // ********** private definitions **********
 
 #define QUEUE_MAX_SIZE                  20                              ///< Max queue size.
+
+#if BL_STACK_ID == 1
+#define FPGA_PAGE_SIZE                  512                             ///< FPGA register pages are 256 bytes.
+#define FPGA_WRITE_CMD_HDR_LEN          5                               ///< FPGA write command header byte length.
+#define FPGA_READ_CMD_HDR_LEN           5                               ///< FPGA read command header byte length.
+#define FPGA_BULK_READ_START_ADDR       0x0200                          ///< Start address for FPGA continuous priority reads.
+#else
 #define FPGA_PAGE_SIZE                  256                             ///< FPGA register pages are 256 bytes.
+#define FPGA_WRITE_CMD_HDR_LEN          4                               ///< FPGA write command header byte length.
+#define FPGA_READ_CMD_HDR_LEN           4                               ///< FPGA read command header byte length.
+#define FPGA_BULK_READ_START_ADDR       0x0100                          ///< Start address for FPGA continuous priority reads.
+#endif
+
 #define FPGA_MAX_READ_SIZE              ( FPGA_PAGE_SIZE - 1 )          ///< FGPA max read size.
 #define FPGA_WRITE_CMD_BUFFER_LEN       ( FPGA_PAGE_SIZE + 8 )          ///< FPGA write command buffer byte length.
 #define FPGA_READ_CMD_BUFFER_LEN        8                               ///< FPGA read command buffer byte length.
@@ -30,26 +42,31 @@
 #define SCI2_TRANSMIT_DMA_REQUEST       29                              ///< Serial port 2 transmit DMA request line.
 
 #define FPGA_CRC_LEN                    2                               ///< FPGA CRC byte length.
-#define FPGA_WRITE_CMD_HDR_LEN          4                               ///< FPGA write command header byte length.
 #define FPGA_WRITE_RSP_HDR_LEN          3                               ///< FPGA write command response header byte length.
+#define FPGA_READ_RSP_HDR_LEN           3                               ///< FPGA read command response header byte length.
 
 #define FPGA_WRITE_CMD_CODE             0x55                            ///< FPGA write command code.
 #define FPGA_WRITE_CMD_ACK              0xA5                            ///< FPGA write command ACK code.
 #define FPGA_READ_CMD_CODE              0x5A                            ///< FPGA read command code.
 #define FPGA_READ_CMD_ACK               0xAA                            ///< FPGA read command ACK code.
 #define FPGA_HEADER_START_ADDR          0x0000                          ///< Start address for FPGA header data.
-#define FPGA_BULK_READ_START_ADDR       0x0100                          ///< Start address for FPGA continuous priority reads.
 #define FPGA_WRITE_START_ADDR           0x000B                          ///< Start address for FPGA continuous priority writes. // TODO does this vary?
-#define FPGA_FLASH_CONTROL_REG_ADDR     0x090E
+
+#if BL_STACK_ID == 1
+#define FPGA_FLASH_CONTROL_REG_ADDR     0x120E                          ///< FPGA flash control register address.
+#define FPGA_MULTI_BOOT_STATUS_ADDR     0x1200                          ///< FPGA multi boot status register address.
+#define FPGA_ICAP2_REG_ADDR             0x1209                          ///< FPGA ICAP 2 command register address.
+#else
+#define FPGA_FLASH_CONTROL_REG_ADDR     0x090E                          ///< FPGA flash control register address.
+#define FPGA_MULTI_BOOT_STATUS_ADDR     0x0900                          ///< FPGA multi boot status register address.
+#define FPGA_ICAP2_REG_ADDR             0x0909                          ///< FPGA ICAP 2 command register address.
+#endif
+
 #define FPGA_FLASH_STATUS_REG_ADDR      0x0900                          ///< FPGA flash status register address.  // TODO remvoe
 #define FPGA_FIFO_COUNT_REG_ADDR        0x0902                          ///< FPGA FIFO count register address.    // TODO remvoe
 #define FPGA_FLASH_DATA_REG_ADDR        0x0A00                          ///< FPGA flash data register address.    // TODO remvoe
-#define FPGA_MULTI_BOOT_STATUS_ADDR     0x0900                          ///< FPGA multi boot status register address.
-#define FPGA_ICAP2_REG_ADDR             0x0909                          ///< FPGA ICAP 2 command register address.
 
 #define FPGA_UPDATE_REGISTER_ADDR       ( FPGA_WRITE_START_ADDR + 4 )   ///< FPGA update register address.
-#define FPGA_READ_CMD_HDR_LEN           4                               ///< FPGA read command header byte length.
-#define FPGA_READ_RSP_HDR_LEN           3                               ///< FPGA read command response header byte length.
 #define FPGA_UPDATE_REQUEST_INDEX       ( FPGA_READ_RSP_HDR_LEN + 1 )   ///< FPGA update request index.                    // TODO Get this value from Noe, make sure the index is the same in all of the stacks
 #define FPGA_FLASH_STATUS_INDEX         ( FPGA_READ_RSP_HDR_LEN + 1 )   ///< FPGA flash status index.
 #define FPGA_FIFO_COUNT_INDEX           ( FPGA_READ_RSP_HDR_LEN + 1 )   ///< FPGA FIFO count index.
@@ -567,11 +584,20 @@
     fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
     fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress );
     fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress );
+#if BL_STACK_ID == 1
     fpgaReadCmdBuffer[ 3 ] = jobSize;
+    fpgaReadCmdBuffer[ 4 ] = 0;
+#else
+    fpgaReadCmdBuffer[ 3 ] = jobSize;
+#endif
     crc                    = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
+#if BL_STACK_ID == 1
+    fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc );
+#else
     fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
     fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
-
+#endif
     // Prep DMA for sending the read cmd and receiving the response
     fpgaJobsQStatus.fpgaCommRead           = FPGA_COMM_READ_IN_PROGRESS;
     fpgaFlashStatus.hasUpdateRegsBeenRqstd = TRUE;
@@ -952,7 +978,12 @@
     fpgaWriteCmdBuffer[ 0 ]              = FPGA_WRITE_CMD_CODE;
     fpgaWriteCmdBuffer[ 1 ]              = GET_LSB_OF_WORD( jobAddress );
     fpgaWriteCmdBuffer[ 2 ]              = GET_MSB_OF_WORD( jobAddress );
+#if BL_STACK_ID == 1
     fpgaWriteCmdBuffer[ 3 ]              = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE;
+    fpgaWriteCmdBuffer[ 4 ]              = 0;
+#else
+    fpgaWriteCmdBuffer[ 3 ]              = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE;
+#endif
     crc                                  = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + jobSize );
     fpgaWriteCmdBuffer[ firstCRCIndex ]  = GET_MSB_OF_WORD( crc );
     fpgaWriteCmdBuffer[ secondCRCIndex ] = GET_LSB_OF_WORD( crc );
@@ -1039,11 +1070,22 @@
     fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
     fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress );
     fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress );
+#if BL_STACK_ID == 1
     fpgaReadCmdBuffer[ 3 ] = jobSize;
+    fpgaReadCmdBuffer[ 4 ] = 0;
+#else
+    fpgaReadCmdBuffer[ 3 ] = jobSize;
+#endif
     crc                    = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
+#if BL_STACK_ID == 1
+    fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc );
+#else
     fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
     fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
 
+#endif
+
     // Prep DMA for sending the read cmd and receiving the response
     fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS;
     fpgaFlashStatus.startTime    = getMSTimerCount();