Index: firmware/source/can.c =================================================================== diff -u -r292265111b911fa79c52bb4589911dfb60c921bf -rfc9a9244cf4288ff0623c3e02455ac565bf60cdd --- firmware/source/can.c (.../can.c) (revision 292265111b911fa79c52bb4589911dfb60c921bf) +++ firmware/source/can.c (.../can.c) (revision fc9a9244cf4288ff0623c3e02455ac565bf60cdd) @@ -254,8 +254,8 @@ } /* Wait */ canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U); - canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x604U & (uint32)0x000007FFU) << (uint32)18U); - canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x604U & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; canREG1->IF2CMD = (uint8) 0xF8U; canREG1->IF2NO = 4U; @@ -273,11 +273,30 @@ } /* Wait */ canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U); - canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x605U & (uint32)0x000007FFU) << (uint32)18U); - canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x605U & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; canREG1->IF1CMD = (uint8) 0xF8U; canREG1->IF1NO = 5U; + /** - Initialize message 6 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x606U & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 6U; + /** - Setup IF1 for data transmission * - Wait until IF1 is ready for use * - Set IF1 control byte