Index: firmware/source/can.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/can.c (.../can.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/can.c (.../can.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -182,326 +182,140 @@ /** - Setup auto bus on timer period */ canREG1->ABOTR = (uint32)0U; - /** - Setup IF1 for data transmission + /** - Initialize message 1 * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration * - Set IF1 control byte + * - Set IF1 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG1->IF1CMD = 0x87U; - /** - Setup IF2 for reading data - * - Wait until IF1 is ready for use - * - Set IF1 control byte + + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x601U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 1U; + + /** - Initialize message 2 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG1->IF2CMD = 0x17U; - /** - Setup bit timing - * - Setup baud rate prescaler extension - * - Setup TSeg2 - * - Setup TSeg1 - * - Setup sample jump width - * - Setup baud rate prescaler - */ - canREG1->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)19U; + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x602U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 2U; - - /** - CAN1 Port output values */ - canREG1->TIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)1U << 2U ) - | (uint32)((uint32)1U << 1U ); - - canREG1->RIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U <<1U ); - - /** - Leave configuration and initialization mode */ - canREG1->CTL &= ~(uint32)(0x00000041U); - - - /** @b Initialize @b CAN2: */ - - /** - Setup control register - * - Disable automatic wakeup on bus activity - * - Local power down mode disabled - * - Disable DMA request lines - * - Enable global Interrupt Line 0 and 1 - * - Disable debug mode - * - Release from software reset - * - Enable/Disable parity or ECC - * - Enable/Disable auto bus on timer - * - Setup message completion before entering debug state - * - Setup normal operation mode - * - Request write access to the configuration registers - * - Setup automatic retransmission of messages - * - Disable error interrupts - * - Disable status interrupts - * - Enter initialization mode + /** - Initialize message 3 + * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF1 control byte + * - Set IF1 message number */ - canREG2->CTL = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)((uint32)0x00000005U << 10U) - | 0x00020043U; + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ - /** - Clear all pending error flags and reset current status */ - canREG2->ES |= 0xFFFFFFFFU; + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x603U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 3U; - /** - Assign interrupt level for messages */ - canREG2->INTMUXx[0U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - canREG2->INTMUXx[1U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - - /** - Setup auto bus on timer period */ - canREG2->ABOTR = (uint32)0U; - - - /** - Setup IF1 for data transmission - * - Wait until IF1 is ready for use - * - Set IF1 control byte + /** - Initialize message 4 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG2->IF1STAT & 0x80U) ==0x80U) + while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG2->IF1CMD = 0x87U; - /** - Setup IF2 for reading data + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x604U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 4U; + + /** - Initialize message 5 * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration * - Set IF1 control byte + * - Set IF1 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG2->IF2STAT & 0x80U) ==0x80U) + while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG2->IF2CMD = 0x17U; - /** - Setup bit timing - * - Setup baud rate prescaler extension - * - Setup TSeg2 - * - Setup TSeg1 - * - Setup sample jump width - * - Setup baud rate prescaler - */ - canREG2->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)19U; + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x605U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 5U; - - /** - CAN2 Port output values */ - canREG2->TIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)1U << 2U ) - | (uint32)((uint32)1U << 1U ); - - canREG2->RIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U <<1U ); - - /** - Leave configuration and initialization mode */ - canREG2->CTL &= ~(uint32)(0x00000041U); - - /** @b Initialize @b CAN3: */ - - /** - Setup control register - * - Disable automatic wakeup on bus activity - * - Local power down mode disabled - * - Disable DMA request lines - * - Enable global Interrupt Line 0 and 1 - * - Disable debug mode - * - Release from software reset - * - Enable/Disable parity or ECC - * - Enable/Disable auto bus on timer - * - Setup message completion before entering debug state - * - Setup normal operation mode - * - Request write access to the configuration registers - * - Setup automatic retransmission of messages - * - Disable error interrupts - * - Disable status interrupts - * - Enter initialization mode + /** - Initialize message 8 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ - canREG3->CTL = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)((uint32)0x00000005U << 10U) - | 0x00020043U; + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ - /** - Clear all pending error flags and reset current status */ - canREG3->ES |= 0xFFFFFFFFU; + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)8U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 8U; - /** - Assign interrupt level for messages */ - canREG3->INTMUXx[0U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - canREG3->INTMUXx[1U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - /** - Setup auto bus on timer period */ - canREG3->ABOTR = (uint32)0U; - /** - Setup IF1 for data transmission * - Wait until IF1 is ready for use * - Set IF1 control byte */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG3->IF1STAT & 0x80U) ==0x80U) + while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG3->IF1CMD = 0x87U; + canREG1->IF1CMD = 0x87U; /** - Setup IF2 for reading data * - Wait until IF1 is ready for use * - Set IF1 control byte */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG3->IF2STAT & 0x80U) ==0x80U) + while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG3->IF2CMD = 0x17U; + canREG1->IF2CMD = 0x17U; /** - Setup bit timing * - Setup baud rate prescaler extension @@ -510,31 +324,34 @@ * - Setup sample jump width * - Setup baud rate prescaler */ - canREG3->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)(uint32)19U; + canREG1->BTR = (uint32)((uint32)0U << 16U) | + (uint32)((uint32)(6U - 1U) << 12U) | + (uint32)((uint32)((3U + 6U) - 1U) << 8U) | + (uint32)((uint32)(4U - 1U) << 6U) | + (uint32)25U; - /** - CAN3 Port output values */ - canREG3->TIOC = (uint32)((uint32)1U << 18U ) + /** - CAN1 Port output values */ + canREG1->TIOC = (uint32)((uint32)1U << 18U ) | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 16U ) | (uint32)((uint32)1U << 3U ) | (uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U ); - canREG3->RIOC = (uint32)((uint32)1U << 18U ) + canREG1->RIOC = (uint32)((uint32)1U << 18U ) | (uint32)((uint32)0U << 17U ) | (uint32)((uint32)0U << 16U ) | (uint32)((uint32)1U << 3U ) | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U << 1U ); + | (uint32)((uint32)0U <<1U ); /** - Leave configuration and initialization mode */ - canREG3->CTL &= ~(uint32)(0x00000041U); + canREG1->CTL &= ~(uint32)(0x00000041U); + + + /** @note This function has to be called before the driver can be used.\n * This function has to be executed in privileged mode.\n */ @@ -1500,110 +1317,105 @@ config_reg->CONFIG_RIOC = canREG1->RIOC; } } -/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the CAN2 configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ +/** @fn void can1HighLevelInterrupt(void) +* @brief CAN1 Level 0 Interrupt Handler */ -/* SourceId : CAN_SourceId_018 */ -/* DesignId : CAN_DesignId_017 */ -/* Requirements : HL_SR224 */ -void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + +/* SourceId : CAN_SourceId_020 */ +/* DesignId : CAN_DesignId_018 */ +/* Requirements : HL_SR221, HL_SR222, HL_SR223 */ +void can1HighLevelInterrupt(void) { - if (type == InitialValue) + uint32 value = canREG1->INT; + uint32 ES_value; + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + + if (value == 0x8000U) { - config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; - config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; - config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; - config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; - config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; - config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; - config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; - config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; - config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + /* Read Error and Status Register*/ + ES_value = canREG1->ES; + + /* Check for Error (PES, Boff, EWarn & EPass) captured */ + if((ES_value & 0x1E0U) != 0U) + { + canErrorNotification(canREG1, ES_value & 0x1E0U); + } + else + { + /* Call General Can notification incase of RxOK, TxOK, PDA, WakeupPnd Interrupt */ + canStatusChangeNotification(canREG1, ES_value & 0x618U); + } } else { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_CTL = canREG2->CTL; - config_reg->CONFIG_ES = canREG2->ES; - config_reg->CONFIG_BTR = canREG2->BTR; - config_reg->CONFIG_TEST = canREG2->TEST; - config_reg->CONFIG_ABOTR = canREG2->ABOTR; - config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[0]; - config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[1]; - config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[2]; - config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[3]; - config_reg->CONFIG_TIOC = canREG2->TIOC; - config_reg->CONFIG_RIOC = canREG2->RIOC; + /** - Setup IF1 for clear pending interrupt flag */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + canREG1->IF1CMD = 0x08U; + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + canREG1->IF1NO = (uint8) value; + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + canMessageNotification(canREG1, value); } + +/* USER CODE BEGIN (42) */ +/* USER CODE END */ + } -/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the CAN3 configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +/** @fn void can1LowLevelInterrupt(void) +* @brief CAN1 Level 1 Interrupt Handler */ -/* SourceId : CAN_SourceId_019 */ -/* DesignId : CAN_DesignId_017 */ -/* Requirements : HL_SR224 */ -void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + +/* SourceId : CAN_SourceId_021 */ +/* DesignId : CAN_DesignId_019 */ +/* Requirements : HL_SR221, HL_SR223 */ +void can1LowLevelInterrupt(void) { - if (type == InitialValue) - { - config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; - config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; - config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; - config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; - config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; - config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; - config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; - config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; - config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; - } - else - { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_CTL = canREG3->CTL; - config_reg->CONFIG_ES = canREG3->ES; - config_reg->CONFIG_BTR = canREG3->BTR; - config_reg->CONFIG_TEST = canREG3->TEST; - config_reg->CONFIG_ABOTR = canREG3->ABOTR; - config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[0]; - config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[1]; - config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[2]; - config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[3]; - config_reg->CONFIG_TIOC = canREG3->TIOC; - config_reg->CONFIG_RIOC = canREG3->RIOC; - } -} + uint32 messageBox = canREG1->INT >> 16U; +/* USER CODE BEGIN (44) */ +/* USER CODE END */ + /** - Setup IF1 for clear pending interrupt flag */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x08U; + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + canREG1->IF1NO = (uint8) messageBox; + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + canMessageNotification(canREG1, messageBox); +/* USER CODE BEGIN (45) */ +/* USER CODE END */ +} + +