Index: firmware/source/etpwm.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/etpwm.c (.../etpwm.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/etpwm.c (.../etpwm.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -82,13 +82,13 @@ etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG1->TBPRD = 1000U; + etpwmREG1->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG1->CMPA = 50U; + etpwmREG1->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG1->CMPB = 50U; + etpwmREG1->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -107,7 +107,7 @@ | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -122,7 +122,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -177,13 +177,13 @@ etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG2->TBPRD = 1000U; + etpwmREG2->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG2->CMPA = 50U; + etpwmREG2->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG2->CMPB = 50U; + etpwmREG2->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -202,7 +202,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -217,7 +217,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -272,13 +272,13 @@ etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG3->TBPRD = 1000U; + etpwmREG3->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG3->CMPA = 50U; + etpwmREG3->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG3->CMPB = 50U; + etpwmREG3->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -297,7 +297,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -312,7 +312,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -368,13 +368,13 @@ etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG4->TBPRD = 1000U; + etpwmREG4->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG4->CMPA = 50U; + etpwmREG4->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG4->CMPB = 50U; + etpwmREG4->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -393,7 +393,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -408,7 +408,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ @@ -454,102 +454,6 @@ etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM5 */ - - /** - Sets high speed time-base clock prescale bits */ - etpwmREG5->TBCTL = (uint16)0U << 7U; - - /** - Sets time-base clock prescale bits */ - etpwmREG5->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG5->TBPRD = 1000U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG5->CMPA = 50U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG5->CMPB = 50U; - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG5->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG5->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG5->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG5->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG5->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG5->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - - /** - Set trip source enable */ - etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG5->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG5->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG5->ETSEL & 0x0007U) != 0U) - { - etpwmREG5->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG5->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG5->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG5->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM6 */ /** - Sets high speed time-base clock prescale bits */ @@ -559,13 +463,13 @@ etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG6->TBPRD = 1000U; + etpwmREG6->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG6->CMPA = 50U; + etpwmREG6->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG6->CMPB = 50U; + etpwmREG6->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ @@ -585,7 +489,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -600,7 +504,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ @@ -657,13 +561,13 @@ etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG7->TBPRD = 1000U; + etpwmREG7->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG7->CMPA = 50U; + etpwmREG7->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG7->CMPB = 50U; + etpwmREG7->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ @@ -683,7 +587,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -698,7 +602,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */