Index: firmware/source/mibspi.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/mibspi.c (.../mibspi.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/mibspi.c (.../mibspi.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -94,7 +94,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 1 */ @@ -105,7 +105,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -116,7 +116,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -127,7 +127,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -477,7 +477,7 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ @@ -537,7 +537,7 @@ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ - | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 25U); /* SOMI[1] */ @@ -570,15 +570,15 @@ | (uint32)((uint32)0U << 0U); /* C2EDELAY */ /** - Data Format 0 */ - mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ + mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ - | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ - | (uint32)((uint32)16U << 0U); /* data word length */ + | (uint32)((uint32)1U << 16U) /* clock phase */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ + | (uint32)((uint32)8U << 0U); /* data word length */ /** - Data Format 1 */ mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ @@ -588,7 +588,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -599,7 +599,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -610,7 +610,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -636,67 +636,67 @@ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)8U << 8U); /* start buffer */ + | (uint32)((uint32)11U << 8U); /* start buffer */ mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ - mibspiREG3->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U; + mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U; - mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); /** - initialize buffer ram */ { i = 0U; -#if (8U > 0U) +#if (11U > 0U) { -#if (8U > 1U) +#if (11U > 1U) - while (i < (8U-1U)) + while (i < (11U-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ - | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)1U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ i++; } #endif @@ -705,7 +705,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ i++; @@ -717,15 +717,15 @@ #if (0U > 1U) - while (i < ((8U+0U)-1U)) + while (i < ((11U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -735,7 +735,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -746,15 +746,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U)-1U)) + while (i < ((11U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -764,7 +764,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -775,15 +775,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -793,7 +793,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -804,15 +804,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -822,7 +822,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -833,15 +833,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -851,7 +851,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -862,15 +862,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -880,7 +880,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -891,15 +891,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -909,7 +909,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } #endif @@ -932,12 +932,12 @@ mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U) | (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ - | (uint32)((uint32)0U << 6U) /* OVRNINT */ - | (uint32)((uint32)0U << 4U) /* BITERR */ - | (uint32)((uint32)0U << 3U) /* DESYNC */ - | (uint32)((uint32)0U << 2U) /* PARERR */ - | (uint32)((uint32)0U << 1U) /* TIMEOUT */ - | (uint32)((uint32)0U << 0U); /* DLENERR */ + | (uint32)((uint32)1U << 6U) /* OVRNINT */ + | (uint32)((uint32)1U << 4U) /* BITERR */ + | (uint32)((uint32)1U << 3U) /* DESYNC */ + | (uint32)((uint32)1U << 2U) /* PARERR */ + | (uint32)((uint32)1U << 1U) /* TIMEOUT */ + | (uint32)((uint32)1U << 0U); /* DLENERR */ /** @b initialize @b MIBSPI3 @b Port */ @@ -1005,12 +1005,12 @@ /* MIBSPI3 set all pins to functional */ - mibspiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */ - | (uint32)((uint32)0U << 1U) /* SCS[1] */ + mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ - | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO */ @@ -1051,7 +1051,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 1 */ @@ -1062,7 +1062,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -1073,7 +1073,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -1084,7 +1084,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -1436,10 +1436,10 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ - | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ @@ -1468,7 +1468,7 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ @@ -1500,10 +1500,10 @@ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 8U) /* ENA */ - | (uint32)((uint32)1U << 9U) /* CLK */ - | (uint32)((uint32)1U << 10U) /* SIMO[0] */ - | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 18U) /* SIMO[2] */ | (uint32)((uint32)1U << 19U) /* SIMO[3] */