Index: firmware/source/sys_startup.c
===================================================================
diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -r850f8042a02fd17ee53b8db24bc2e3d17bbb9c7f
--- firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 792764062d7b7826af10e030277f18379af4fcd1)
+++ firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 850f8042a02fd17ee53b8db24bc2e3d17bbb9c7f)
@@ -64,6 +64,7 @@
 
 #include "errata_SSWF021_45.h"
 /* USER CODE BEGIN (1) */
+#include "reg_crc.h"
 /* USER CODE END */
 
 
@@ -417,18 +418,6 @@
 
 /* USER CODE BEGIN (40) */
 /* USER CODE END */
-
-    /* Test the CPU ECC mechanism for RAM accesses.
-     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
-     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
-     * in the ECC causes a data abort exception. The data abort handler is written to look for
-     * deliberately caused exception and to return the code execution to the instruction
-     * following the one that caused the abort.
-     */
-    checkRAMECC();
-
-/* USER CODE BEGIN (41) */
-/* USER CODE END */
 /* USER CODE BEGIN (43) */
 /* USER CODE END */
 
@@ -616,9 +605,6 @@
 /* USER CODE BEGIN (72) */
 /* USER CODE END */
     
-    /* Enable IRQ offset via Vic controller */
-    _coreEnableIrqVicOffset_();
-    
 
 /* USER CODE BEGIN (73) */
 /* USER CODE END */
@@ -627,6 +613,14 @@
     vimInit();    
 
 /* USER CODE BEGIN (74) */
+    // Shuffle IRQ priorities per design requirements
+    vimChannelMap( 3, 40, &rtiCompare1Interrupt );
+    vimChannelMap( 5, 64, &rtiCompare3Interrupt );
+    vimChannelMap( 13, 3, &linHighLevelInterrupt );
+    vimChannelMap( 16, 16, &can1HighLevelInterrupt );
+    vimChannelMap( 29, 13, &can1LowLevelInterrupt );
+    vimChannelMap( 40, 5, &dmaBTCAInterrupt );
+    vimChannelMap( 64, 29, &sciHighLevelInterrupt );
 /* USER CODE END */
 
     /* Configure system response to error conditions signaled to the ESM group1 */