Index: firmware/.settings/org.eclipse.core.resources.prefs
===================================================================
diff -u -rabb9687e52d9db5df1abe7626ba04a6d431ba823 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/.settings/org.eclipse.core.resources.prefs	(.../org.eclipse.core.resources.prefs)	(revision abb9687e52d9db5df1abe7626ba04a6d431ba823)
+++ firmware/.settings/org.eclipse.core.resources.prefs	(.../org.eclipse.core.resources.prefs)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -12,3 +12,16 @@
 encoding//Debug/source/subdir_rules.mk=UTF-8
 encoding//Debug/source/subdir_vars.mk=UTF-8
 encoding//Debug/sources.mk=UTF-8
+encoding//Release/App/Modes/subdir_rules.mk=UTF-8
+encoding//Release/App/Modes/subdir_vars.mk=UTF-8
+encoding//Release/App/Services/FlashAPI/subdir_rules.mk=UTF-8
+encoding//Release/App/Services/FlashAPI/subdir_vars.mk=UTF-8
+encoding//Release/App/Services/subdir_rules.mk=UTF-8
+encoding//Release/App/Services/subdir_vars.mk=UTF-8
+encoding//Release/App/Tasks/subdir_rules.mk=UTF-8
+encoding//Release/App/Tasks/subdir_vars.mk=UTF-8
+encoding//Release/makefile=UTF-8
+encoding//Release/objects.mk=UTF-8
+encoding//Release/source/subdir_rules.mk=UTF-8
+encoding//Release/source/subdir_vars.mk=UTF-8
+encoding//Release/sources.mk=UTF-8
Index: firmware/App/Services/Download.c
===================================================================
diff -u -r012573b1913d1bfd2357acfadcad6bb20b295ad9 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/App/Services/Download.c	(.../Download.c)	(revision 012573b1913d1bfd2357acfadcad6bb20b295ad9)
+++ firmware/App/Services/Download.c	(.../Download.c)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -85,6 +85,17 @@
     SWUpdateCommandState = UPDATE_CMD_IDLE;
 }
 
+void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus )
+{
+    SW_UPDATE_RESP_STATUS_T resp;
+
+    BOOL status = FALSE; // TODO do we need this?
+
+    prepareResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus, &resp );
+    status = sendAckNackStatusFromFirmware( (U08*)&resp );
+    clearCommBuffer( thisStackMailBox );
+}
+
 // ********** private functions **********
 
 static void processIncomingCmdMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox )
@@ -132,7 +143,7 @@
 {
     S32 bytesInBuffer = getNumberOfBytesInBuffer( mailBox );
 
-    if ( bytesInBuffer >= NUM_OF_CAN_BYTES_FOR_UPDATE )
+    if ( bytesInBuffer == NUM_OF_CAN_BYTES_FOR_UPDATE )
     {
         SW_UPDATE_RESP_STATUS_T resp;
 
@@ -167,10 +178,17 @@
                     break;
             }
         }
+        else
+        {
+            prepareResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus, &resp );
+            status = sendAckNackStatusFromFirmware( (U08*)&resp ); // TODO do we have to retry if send failed?
+            clearCommBuffer( mailBox ); // TODo does this need to be here? How about resync?
+            //clearSWUpdateBuffer(); // TODO uncomment
+        }
 
-        prepareResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus, &resp );
-        status = sendAckNackStatusFromFirmware( (U08*)&resp ); // TODO do we have to retry if send failed?
-        clearCommBuffer( mailBox ); // TODo does this need to be here? How about resync?
+        //prepareResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus, &resp );
+        //status = sendAckNackStatusFromFirmware( (U08*)&resp ); // TODO do we have to retry if send failed?
+        //clearCommBuffer( mailBox ); // TODo does this need to be here? How about resync?
         //clearSWUpdateBuffer(); // TODO uncomment
     }
 }
@@ -192,16 +210,23 @@
 
 static ACK_NACK_STATUS_T handleFirmwareUpdate( void )
 {
-    ACK_NACK_STATUS_T ackStatus = NACK;
+    SW_UPDATE_RESP_STATUS_T resp;
 
+    ACK_NACK_STATUS_T ackStatus = ACK;
+    BOOL status                 = FALSE;
+
     if ( SWUpdateRCVStatus.cyberIndex != SW_UPDATE_FINAL_MSG_INDEX )
     {
         _disable_IRQ();
-        BOOL status = handleUpdatingFlash( SWUpdateRCVStatus.SWUpdateBuffer );
-        ackStatus   = ( TRUE == status ? ACK : NACK );
+        status    = handleUpdatingFlash( SWUpdateRCVStatus.SWUpdateBuffer );
+        ackStatus = ( TRUE == status ? ACK : NACK );
         _enable_IRQ();
     }
 
+    prepareResponseMessage( SWUpdateRCVStatus.msgID, ackStatus, &resp );
+    status = sendAckNackStatusFromFirmware( (U08*)&resp ); // TODO do we have to retry if send failed?
+    clearCommBuffer( thisStackMailBox ); // TODo does this need to be here? How about resync?
+
     return ackStatus;
 }
 
@@ -258,6 +283,10 @@
             }
         }
     }
+    //else
+    {
+        BOOL d = FALSE;
+    }
 
     return ackStatus;
 }
Index: firmware/App/Services/Download.h
===================================================================
diff -u -r9e2779d825ea7e7b3445fa365f7bc2206fc0613a -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/App/Services/Download.h	(.../Download.h)	(revision 9e2779d825ea7e7b3445fa365f7bc2206fc0613a)
+++ firmware/App/Services/Download.h	(.../Download.h)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -18,4 +18,6 @@
 
 void clearSWUpdateCommandState( void );
 
+void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus );
+
 #endif
Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r012573b1913d1bfd2357acfadcad6bb20b295ad9 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 012573b1913d1bfd2357acfadcad6bb20b295ad9)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -11,6 +11,7 @@
 #include "sys_dma.h"
 
 #include "Comm.h"
+#include "Download.h"
 #include "FPGA.h"
 #include "Timers.h"
 #include "Utilities.h"
@@ -38,9 +39,10 @@
 #define FPGA_BULK_READ_START_ADDR       0x0100                  ///< Start address for FPGA continuous priority reads.
 #define FPGA_WRITE_START_ADDR           0x000B                  ///< Start address for FPGA continuous priority writes. // TODO does this vary?
 #define FPGA_FLASH_CONTROL_REG_ADDR     0x090E
-#define FPGA_FLASH_STATUS_REG_ADDR      0x0900                  ///< FPGA flash status register address.
-#define FPGA_FIFO_COUNT_REG_ADDR        0x0902                  ///< FPGA FIFO count register address.
-#define FPGA_FLASH_DATA_REG_ADDR        0x0A00                  ///< FPGA flash data register address.
+#define FPGA_FLASH_STATUS_REG_ADDR      0x0900                  ///< FPGA flash status register address.  // TODO remvoe
+#define FPGA_FIFO_COUNT_REG_ADDR        0x0902                  ///< FPGA FIFO count register address.    // TODO remvoe
+#define FPGA_FLASH_DATA_REG_ADDR        0x0A00                  ///< FPGA flash data register address.    // TODO remvoe
+#define FPGA_MULTI_BOOT_STATUS_ADDR     0x0900                  ///< FPGA multi boot status register address.
 #define FPGA_ICAP2_REG_ADDR             0x0909                  ///< FPGA ICAP 2 command register address.
 
 #define FPGA_UPDATE_REGISTER_ADDR       ( FPGA_WRITE_START_ADDR + 4 )
@@ -76,9 +78,7 @@
     FPGA_RESET_FLASH,
     FPGA_ERASE_FIFO,
     FPGA_ENABLE_FLASH,
-    FPGA_CHECK_ERASE_FIFO_STATUS,
-    FPGA_CHECK_FLASH_READY_STATUS,
-    FPGA_CHECK_FIFO_COUNT,
+    FPGA_READ_MULTI_BOOT_STATUS,
     FPGA_FLASH_WRITE_DATA,
     FPGA_SELF_CONFIGURE,
     NUM_OF_FPGA_JOBS,
@@ -117,6 +117,7 @@
 typedef struct
 {
     BOOL isFlashErased;
+    U16 fifoRemainingCount;
     FPGA_FLASH_STATE_T fpgaFlashState;
     U32 startTime;
 } FPGA_FLASH_STATUS_T;
@@ -153,6 +154,9 @@
 static U32 fpgaDataLenToWrite;
 
 static U32 TESTREMOVE = 0; // TODO remove
+static U32 countRemove = 0; // TODO remove
+static U32 nonzeroCounter = 0; // TODO remove
+static U16 nonZeroCount[100]; // TODO remove
 
 static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61, 0xFF };  // TODO update with the real FPGA IDs
 static const U16 DISABLE_UPDATE_REG_CMD            = 5; // TODO what is this value? 0?
@@ -168,19 +172,15 @@
   { FPGA_FLASH_CONTROL_REG_ADDR,    sizeof( U08 ),                 (U08*)&FPGA_RESET_FLASH_CMD,    TRUE  },        // FPGA_RESET_FLASH
   { FPGA_FLASH_CONTROL_REG_ADDR,    sizeof( U08 ),                 (U08*)&FPGA_ERASE_FIFO_CMD,     TRUE  },        // FPGA_ERASE_FIFO
   { FPGA_FLASH_CONTROL_REG_ADDR,    sizeof( U08 ),                 (U08*)&FPGA_ENABLE_FLASH_CMD,   TRUE  },        // FPGA_ENABLE_FLASH
-  { FPGA_FLASH_STATUS_REG_ADDR,     sizeof( U16 ),                 0,                              FALSE },        // FPGA_CHECK_ERASE_FIFO_STATUS
-  { FPGA_FLASH_STATUS_REG_ADDR,     sizeof( U16 ),                 0,                              FALSE },        // FPGA_CHECK_FLASH_READY_STATUS
-  { FPGA_FIFO_COUNT_REG_ADDR,       sizeof( U16 ),                 0,                              FALSE },        // FPGA_CHECK_FIFO_COUNT
+  { FPGA_MULTI_BOOT_STATUS_ADDR,    sizeof( U32 ),                 0,                              FALSE },        // FPGA_READ_MULTI_BOOT_STATUS
   { FPGA_FLASH_DATA_REG_ADDR,       SW_UPDATE_FLASH_BUFFER_SIZE,   fpgaDataToWriteBuffer,          TRUE  },        // FPGA_FLASH_WRITE_DATA
   { FPGA_ICAP2_REG_ADDR,            sizeof( U08 ),                 (U08*)&FPGA_SELF_CONFIG_CMD,    TRUE  }         // FPGA_SELF_CONFIGURE
 };
 
 static void initDMA( void );
 static void consumeUnexpectedData( void );
 static BOOL processFPGAReceivedData( void );
-static BOOL isFPGAEraseFlashStatusOk( void );
-static BOOL isFPGAFlashStatusOk( void );
-static BOOL isFPGAFIFOStatusOk( void );
+static void processFPGAFlashStatus( void );
 
 static void setupDMAForReadResp( U32 bytes2Receive );
 static void setupDMAForReadCmd( U32 bytes2Transmit );
@@ -215,6 +215,7 @@
 
     enqueue( FPGA_READ_HEADER );
     enqueue( FPGA_READ_UPDATE_REG );
+    enqueue( FPGA_READ_MULTI_BOOT_STATUS );
 
     fpgaState                = FPGA_IDLE_STATE;
     fpgaUpdateRegisterStatus = 0;
@@ -295,10 +296,9 @@
 {
     if ( FALSE == isQueueFull() )
     {
-        //enqueue( FPGA_RESET_FLASH );
-        //enqueue( FPGA_ERASE_FIFO );
+        enqueue( FPGA_RESET_FLASH );
+        enqueue( FPGA_ERASE_FIFO );
         enqueue( FPGA_ENABLE_FLASH );
-        //enqueue( FPGA_CHECK_ERASE_FIFO_STATUS );
     }
 }
 
@@ -308,12 +308,8 @@
     {
         memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE );
 
-        //enqueue( FPGA_CHECK_FLASH_READY_STATUS );
-        //enqueue( FPGA_CHECK_FIFO_COUNT );
         enqueue( FPGA_FLASH_WRITE_DATA );
-        //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only
-        //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only
-        //enqueue( FPGA_CHECK_FIFO_COUNT ); // TODO remove for testing only
+
         fpgaDataLenToWrite = len;
         memcpy( fpgaDataToWriteBuffer, data, len );
 
@@ -448,18 +444,10 @@
             fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ];
             break;
 
-        case FPGA_CHECK_ERASE_FIFO_STATUS:
-            status = isFPGAEraseFlashStatusOk();
+        case FPGA_READ_MULTI_BOOT_STATUS:
+            processFPGAFlashStatus();
             break;
 
-        case FPGA_CHECK_FLASH_READY_STATUS:
-            status = isFPGAFlashStatusOk();
-            break;
-
-        case FPGA_CHECK_FIFO_COUNT:
-            status = isFPGAFIFOStatusOk();
-            break;
-
         default:
             // Do nothing
             break;
@@ -468,58 +456,40 @@
     return status;
 }
 
-static BOOL isFPGAEraseFlashStatusOk( void )
+static void processFPGAFlashStatus( void )
 {
-    U08 jobSize      = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize;
-    U16 flashStatus  = 0;
-    BOOL eraseStatus = FALSE;
+    U16 flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] );
+    U16 fifoStatus  = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) ],
+                                          fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) - 1 ] );
 
-    memcpy( &flashStatus, &fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], jobSize );
+    fpgaFlashStatus.fpgaFlashState     = FPGA_UPDATE_NOT_READY;
+    fpgaFlashStatus.isFlashErased      = FALSE;
+    fpgaFlashStatus.fifoRemainingCount = FPGA_FIFO_SIZE_BYTES - ( FPGA_FIFO_COUNT_MASK & fifoStatus );
 
     if ( ( flashStatus & FPGA_ERASE_FIFO_CMD_OK ) == FPGA_ERASE_FIFO_CMD_OK )
     {
         fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY;
-        eraseStatus                    = TRUE;
+        fpgaFlashStatus.isFlashErased  = TRUE;
     }
 
-    return eraseStatus;
-}
-
-static BOOL isFPGAFlashStatusOk( void )
-{
-    U16 flashStatus    = 0;
-    BOOL flashStatusOk = FALSE;
-
-    flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ],
-                                      fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] );
-
     if ( ( flashStatus & FPGA_FLASH_STATUS_OK ) == FPGA_FLASH_STATUS_OK )
     {
         fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY;
-        flashStatusOk                  = TRUE;
     }
 
-    return flashStatusOk;
-}
-
-static BOOL isFPGAFIFOStatusOk( void )
-{
-    U16 remFIFOCount = 0;
-    BOOL isStatusOk  = FALSE;
-
-    U16 word = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ],
-                                   fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] );
-
-    U16 test  = FPGA_FIFO_COUNT_MASK & word;
-    remFIFOCount = FPGA_FIFO_SIZE_BYTES - test;
-
-    if ( remFIFOCount >= SW_UPDATE_FLASH_BUFFER_SIZE )
+    if ( fpgaFlashStatus.fifoRemainingCount >= SW_UPDATE_FLASH_BUFFER_SIZE )
     {
-        isStatusOk = TRUE;
-        //fpgaFlashStatus.fpgaFlashState =
+        fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY;
     }
+    else
+    {
+        fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_FIFO_FULL;
+    }
 
-    return isStatusOk;
+    if ( fpgaFlashStatus.fifoRemainingCount < FPGA_FIFO_SIZE_BYTES ) // TODO remove
+    {
+        BOOL dara = FALSE;
+    }
 }
 
 static void setupDMAForReadResp( U32 bytes2Receive )
@@ -675,14 +645,22 @@
 {
     FPGA_STATE_T state = FPGA_IDLE_STATE;
 
-    if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 )
+    if ( 0 == fpgaJobsQStatus.fpgaJobsQueueCount )
     {
-        dequeue();
-
-        state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE );
+        enqueue( FPGA_READ_MULTI_BOOT_STATUS );
     }
 
+    dequeue();
+
+    state = ( FALSE == JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaIsJobWrite ? FPGA_READ_FROM_FPGA_STATE : FPGA_WRITE_TO_FPGA_STATE );
+
     // TODo remove
+    if ( ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) && ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) )
+    {
+        nonZeroCount[ nonzeroCounter ] = fpgaFlashStatus.fifoRemainingCount;
+        nonzeroCounter++;
+    }
+
     if ( FPGA_SELF_CONFIGURE == fpgaJobsQStatus.fpgaCurrentJob )
     {
         BOOL test = FALSE;
@@ -756,10 +734,13 @@
             // Does the FPGA response CRC checkout?
             if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) )
             {
-                if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob )  // TODO REMOVE
+                if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob )
                 {
-                    TESTREMOVE += 1; //fpgaDataLenToWrite;
-                    //countRemove += 1;
+                    fpgaFlashStatus.fpgaFlashState = FPGA_UPDATE_READY;
+                    sendFPGAAckNackStatus( ACK );
+
+                    TESTREMOVE += fpgaDataLenToWrite;// TODO REMOVE
+                    countRemove += 1;// TODO REMOVE
                 }
 
                 // CRC passed
@@ -795,6 +776,7 @@
 
     // Prep DMA for sending the read cmd and receiving the response
     fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS;
+    fpgaFlashStatus.startTime    = getMSTimerCount();
 
     setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) );
     setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) );
@@ -823,11 +805,16 @@
 
                 memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN );
 
-                state = ( TRUE == status ? FPGA_IDLE_STATE : FPGA_READ_FROM_FPGA_STATE ); // TODO have a limit
+                state = FPGA_IDLE_STATE;
             }
         }
     }
 
+    if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) )
+    {
+        state = FPGA_IDLE_STATE;
+    }
+
     resetFPGACommFlags();
 
     // Should not be any data received at this time
Index: firmware/BL.dil
===================================================================
diff -u -r012573b1913d1bfd2357acfadcad6bb20b295ad9 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/BL.dil	(.../BL.dil)	(revision 012573b1913d1bfd2357acfadcad6bb20b295ad9)
+++ firmware/BL.dil	(.../BL.dil)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -1,4 +1,4 @@
-# RM46L852PGE 09/10/24 15:28:09
+# RM46L852PGE 09/23/24 12:06:34
 # 
 ARCH=RM46L852PGE
 # 
@@ -139,7 +139,7 @@
 DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0
-DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08003000
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08002800
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109
@@ -407,7 +407,7 @@
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08005000
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08002c00
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt
@@ -435,7 +435,7 @@
 DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11
 DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08005800
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08003400
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0
@@ -502,7 +502,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt
 DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATEVALUE.VALUE=0x5
 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1
-DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00002000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0
@@ -549,14 +549,14 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt
-DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00002000
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000400
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt
-DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00005800
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00003400
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC
 DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
@@ -628,7 +628,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt
 DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
-DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002a800
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002cc00
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
@@ -793,7 +793,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29
 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1
 DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000
-DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000400
 DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0
@@ -925,8 +925,8 @@
 DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800
 DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08005400
-DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08003000
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08002000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ
@@ -1134,7 +1134,7 @@
 DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF
 DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00
-DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002000
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002400
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt
 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000
@@ -1184,7 +1184,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt
 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1
 DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000400
-DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00001000
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000400
 DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef
Index: firmware/include/sys_core.h
===================================================================
diff -u -rdeef095c63fe86de42a7e052e1b9985b0118b02e -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/include/sys_core.h	(.../sys_core.h)	(revision deef095c63fe86de42a7e052e1b9985b0118b02e)
+++ firmware/include/sys_core.h	(.../sys_core.h)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -64,7 +64,7 @@
 *
 *	@note: Use this macro for USER Mode Stack length (in bytes)
 */
-#define USER_STACK_LENGTH   0x00001000U
+#define USER_STACK_LENGTH   0x00002000U
 
 /** @def SVC_STACK_LENGTH
 *   @brief SVC Mode Stack length (in bytes)
@@ -73,7 +73,7 @@
 *
 *	@note: Use this macro for SVC Mode Stack length (in bytes)
 */
-#define SVC_STACK_LENGTH    0x00001000U
+#define SVC_STACK_LENGTH    0x00000400U
 
 /** @def FIQ_STACK_LENGTH
 *   @brief FIQ Mode Stack length (in bytes)
@@ -82,7 +82,7 @@
 *
 *	@note: Use this macro for FIQ Mode Stack length (in bytes)
 */
-#define FIQ_STACK_LENGTH    0x00001000U
+#define FIQ_STACK_LENGTH    0x00000400U
 
 /** @def IRQ_STACK_LENGTH
 *   @brief IRQ Mode Stack length (in bytes)
@@ -91,7 +91,7 @@
 *
 *	@note: Use this macro for IRQ Mode Stack length (in bytes)
 */
-#define IRQ_STACK_LENGTH    0x00002000U
+#define IRQ_STACK_LENGTH    0x00000400U
 
 /** @def ABORT_STACK_LENGTH
 *   @brief ABORT Mode Stack length (in bytes)
Index: firmware/source/sys_core.asm
===================================================================
diff -u -rda12d1065b9bc93d30500255d8b986f00d1bdd69 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/source/sys_core.asm	(.../sys_core.asm)	(revision da12d1065b9bc93d30500255d8b986f00d1bdd69)
+++ firmware/source/sys_core.asm	(.../sys_core.asm)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -160,12 +160,12 @@
         ldr   sp,       userSp
         bx    lr
 
-userSp  .word 0x08000000+0x00001000
-svcSp   .word 0x08000000+0x00001000+0x00001000
-fiqSp   .word 0x08000000+0x00001000+0x00001000+0x00001000
-irqSp   .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000
-abortSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400
-undefSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400+0x00000400
+userSp  .word 0x08000000+0x00002000
+svcSp   .word 0x08000000+0x00002000+0x00000400
+fiqSp   .word 0x08000000+0x00002000+0x00000400+0x00000400
+irqSp   .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400
+abortSp .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400+0x00000400
+undefSp .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400+0x00000400+0x00000400
 
     .endasmfunc
 
Index: firmware/source/sys_link.cmd
===================================================================
diff -u -rf100557efc2f7916054a63bbafb187d8017914d0 -ra5cbf07811efee3c038a550f251d3daefff2bf63
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision f100557efc2f7916054a63bbafb187d8017914d0)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision a5cbf07811efee3c038a550f251d3daefff2bf63)
@@ -56,8 +56,8 @@
 {
     VECTORS (X)  : origin=0x00000000 length=0x00000020
     FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
-    STACKS  (RW) : origin=0x08000000 length=0x00005800
-    RAM     (RW) : origin=0x08005800 length=0x0002a800
+    STACKS  (RW) : origin=0x08000000 length=0x00003400
+    RAM     (RW) : origin=0x08003400 length=0x0002cc00
 
 /* USER CODE BEGIN (2) */
 /* USER CODE END */