Index: firmware/App/Modes/ModeStandby.c =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/App/Modes/ModeStandby.c (.../ModeStandby.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -19,7 +19,7 @@ // ********** private definitions ********** -#define WAIT_FOR_UPDATE_FROM_UI_MS 3000 ///< Wait for update timeout in milliseconds. +#define WAIT_FOR_UPDATE_FROM_UI_MS 1000 // TODO make this 3 seconds ///< Wait for update timeout in milliseconds. // ********** private data ********** Index: firmware/App/Modes/ModeUpdate.c =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Modes/ModeUpdate.c (.../ModeUpdate.c) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/App/Modes/ModeUpdate.c (.../ModeUpdate.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -48,8 +48,6 @@ // Clear the NV status to start from the start address of the firmware clearSWUpdateNVStatus(); // TODO clear FPGA clear stuff here - // Got the update command so we are in the update mode. Clear the command - clearSWUpdateSpecs(); return updateCurrentState; } Index: firmware/App/Services/Download.c =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Services/Download.c (.../Download.c) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/App/Services/Download.c (.../Download.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -78,7 +78,7 @@ static void handleIncomingCmdMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox ); static void handleIncomingUpdateMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox ); static void handleIncomingBroadcastMessage( SW_UPDATE_CAN_MAIL_BOX_T mailBox ); -static void prepareAndSendFWResponseMessage( U16 respOfMsgID, ACK_NACK_STATUS_T ackNack ); +static void prepareAndSendBootLoaderResponseMessage( U16 respOfMsgID, ACK_NACK_STATUS_T ackNack ); static void clearSWUpdateBuffer( void ); static ACK_NACK_STATUS_T handleFirmwareUpdate( void ); static ACK_NACK_STATUS_T handleFPGAUpdate( void ); @@ -168,7 +168,7 @@ { SW_UPDATE_CAN_MAIL_BOX_T thisStackMailBox = RECEIVE_MSG_ID[ BL_STACK_ID ][ FW_STACKS_RCV_MAIL_BOX_INDEX ]; - prepareAndSendFWResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus ); + prepareAndSendBootLoaderResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus ); clearCommBuffer( thisStackMailBox ); } @@ -185,7 +185,15 @@ return SWUpdateLastBroadcastTimeMS; } -U08 getTempRemoveMSGID() +/*********************************************************************//** + * @brief + * The getCurrentUpdateMessageID function returns the current update message + * ID that has been received with update payload. + * @details \b Inputs: SWUpdateRCVStatus + * @details \b Outputs: none + * @return the current update message ID with update payload + *************************************************************************/ +U16 getCurrentUpdateMessageID() { return SWUpdateRCVStatus.msgID; } @@ -235,7 +243,7 @@ } // Send the result of the command received - prepareAndSendFWResponseMessage( msgID, ackStatus ); + prepareAndSendBootLoaderResponseMessage( msgID, ackStatus ); clearCommBuffer( mailBox ); } } @@ -288,10 +296,13 @@ { case UPDATE_FIRMWARE: ackStatus = handleFirmwareUpdate(); + // Send the ack/nack status immediately because the other processes are blocked + prepareAndSendBootLoaderResponseMessage( msgID, ackStatus ); break; case UPDATE_FPGA: ackStatus = handleFPGAUpdate(); + // Do not send the ack/nack immediately. FPGA takes longer to respond and it will through other functions break; default: @@ -300,7 +311,6 @@ } } - prepareAndSendFWResponseMessage( msgID, ackStatus ); clearCommBuffer( mailBox ); clearSWUpdateBuffer(); } @@ -341,15 +351,15 @@ /*********************************************************************//** * @brief - * The prepareAndSendFWResponseMessage function prepares the message body that is - * used to respond to the updater app and sends it. + * The prepareAndSendBootLoaderResponseMessage function prepares the message + * body that is used to respond to the updater app and sends it. * @details \b Inputs: none * @details \b Outputs: none * @param message ID that is being responded for * @param ack nack status * @return none *************************************************************************/ -static void prepareAndSendFWResponseMessage( U16 respOfMsgID, ACK_NACK_STATUS_T ackNack ) +static void prepareAndSendBootLoaderResponseMessage( U16 respOfMsgID, ACK_NACK_STATUS_T ackNack ) { SW_UPDATE_RESP_STATUS_T resp; U32 calcCRC = 0; @@ -427,7 +437,7 @@ } else { - prepareAndSendFWResponseMessage( SWUpdateRCVStatus.msgID, ACK ); + prepareAndSendBootLoaderResponseMessage( SWUpdateRCVStatus.msgID, ACK ); } return ackStatus; Index: firmware/App/Services/Download.h =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Services/Download.h (.../Download.h) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/App/Services/Download.h (.../Download.h) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -31,7 +31,7 @@ U32 getLastBroadcastMessageTimeStampMS( void ); -U08 getTempRemoveMSGID(); // TODO remove or make is permanent +U16 getCurrentUpdateMessageID(); /**@}*/ Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rb1729daefa724d159fa59448cbc87dea54e982d7 -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision b1729daefa724d159fa59448cbc87dea54e982d7) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -56,15 +56,16 @@ #define FPGA_FLASH_CONTROL_REG_ADDR 0x120E ///< FPGA flash control register address. #define FPGA_MULTI_BOOT_STATUS_ADDR 0x1200 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x1209 ///< FPGA ICAP 2 command register address. +#define FPGA_FLASH_DATA_REG_ADDR 0x1400 ///< FPGA flash data register address. #else #define FPGA_FLASH_CONTROL_REG_ADDR 0x090E ///< FPGA flash control register address. #define FPGA_MULTI_BOOT_STATUS_ADDR 0x0900 ///< FPGA multi boot status register address. #define FPGA_ICAP2_REG_ADDR 0x0909 ///< FPGA ICAP 2 command register address. +#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. #endif #define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe #define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe -#define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. // TODO remvoe #define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) ///< FPGA update register address. #define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA update request index. // TODO Get this value from Noe, make sure the index is the same in all of the stacks @@ -96,7 +97,7 @@ typedef enum { FPGA_READ_HEADER = 0, ///< FPGA read header. - FPGA_READ_UPDATE_REG, ///< FPGA read update request register. + FPGA_READ_UPDATE_REG, // TODO remove? ///< FPGA read update request register. FPGA_WRITE_UPDATE_REG, ///< FPGA write to update request register. FPGA_RESET_FLASH, ///< FPGA reset flash. FPGA_ERASE_FIFO, ///< FPGA erase FIFO. @@ -140,6 +141,18 @@ FPGA_COMM_STATE_T fpgaCommWrite; ///< FPGA DMA write command state. } FPGA_JOBS_Q_STATUS_T; +/// FPGA read registers status structure +typedef struct +{ + U16 flashStatus; ///< FPGA flash status. + U16 fifoCount; ///< FPGA FIFO count. + U32 icape2DataIn; ///< FPGA ICAPE2 datain. + U08 icape2Address; ///< FPGA ICAPE2 address. + U08 icape2Cmd; ///< FPGA ICAPE2 command. + U32 icape2DataOut; ///< FPGA ICAPE2 dataout. + U08 flashIntCtrlReg; ///< FPGA flash interface control register. +} FPGA_READ_REGS_T; + /// FPGA flash status structure typedef struct { @@ -182,6 +195,7 @@ static U08 fpgaUpdateRegisterStatus; ///< FPGA update register status. static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; ///< FPGA jobs queue status. static FPGA_FLASH_STATUS_T fpgaFlashStatus; ///< FPGA flash status. +static FPGA_READ_REGS_T fpgaReadRegsStatus; ///< FGPA read registers status. static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; ///< FPGA data to write to FPGA flash buffer. static U32 fpgaDataLenToWrite; ///< FPGA data length to write to FPGA. @@ -190,9 +204,9 @@ static U08 tempACkStatus = 0; // TODO remove /// FPGA stack ID for TD, DD -static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs +static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs // TODO remove // TODO what is this value? 0? -static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. +static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. // TODO remove static const U08 FPGA_RESET_FLASH_CMD = 0x01; ///< FPGA reset flash command. static const U08 FPGA_ERASE_FIFO_CMD = 0x08; ///< FPGA erase FIFO command. static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; ///< FPGA enable flash command. @@ -201,12 +215,14 @@ /// FPGA jobs specifications. static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER - { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // FPGA_READ_UPDATE_REG + { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // TODO remove // FPGA_READ_UPDATE_REG { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), (U08*)&DISABLE_UPDATE_REG_CMD, TRUE }, // FPGA_WRITE_UPDATE_REG + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH - { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( U32 ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS + { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( FPGA_READ_REGS_T ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE }; @@ -250,15 +266,21 @@ *************************************************************************/ void initFPGA( void ) { - memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); + memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); memset( &fpgaJobsQStatus, 0x0, sizeof( FPGA_JOBS_Q_STATUS_T ) ); memset( &fpgaFlashStatus, 0x0, sizeof( FPGA_FLASH_STATUS_T ) ); + // initialize fpga comm buffers + memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN ); + memset( &fpgaReadCmdBuffer, 0, FPGA_READ_CMD_BUFFER_LEN ); + memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); + memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); + initDMA(); consumeUnexpectedData(); enqueue( FPGA_READ_HEADER ); - enqueue( FPGA_READ_UPDATE_REG ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); fpgaState = FPGA_IDLE_STATE; fpgaUpdateRegisterStatus = 0; @@ -273,22 +295,17 @@ *************************************************************************/ void execFPGA( void ) { - if ( TRUE == fpgaFlashStatus.hasUpdateRegsBeenRqstd ) - { - processFPGAFlashRegistersRead(); - } - // TODO test code remove - //U08 data[8]; - //data[0] = getTempRemoveMSGID(); - //data[1] = (U08)fpgaState; - //data[2] = GET_LSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - //data[3] = GET_MSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - //data[4] = GET_LSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - //data[5] = GET_MSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - //data[6] = tempACkStatus; - //data[7] = (U08)fpgaFlashStatus.isFlashStatusOk; - //broadcastDataTestRemove(data); + U08 data[8]; + data[0] = GET_LSB_OF_WORD( getCurrentUpdateMessageID() ); + data[1] = GET_MSB_OF_WORD( getCurrentUpdateMessageID() ); + data[2] = GET_LSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); + data[3] = GET_MSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); + data[4] = GET_LSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); + data[5] = GET_MSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); + data[6] = fpgaJobsQStatus.fpgaCurrentJob; + data[7] = (U08)fpgaState; + broadcastDataTestRemove(data); // TODO test code remove switch( fpgaState ) @@ -333,7 +350,6 @@ if ( FPGA_COMM_WRITE_IN_PROGRESS == fpgaJobsQStatus.fpgaCommWrite ) { fpgaJobsQStatus.fpgaCommWrite = FPGA_COMM_WRITE_RESP_RECEIVED; - requestFlashRegistersStatus(); } else if ( FPGA_COMM_READ_IN_PROGRESS == fpgaJobsQStatus.fpgaCommRead ) { @@ -585,8 +601,8 @@ fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); #if BL_STACK_ID == 1 - fpgaReadCmdBuffer[ 3 ] = jobSize; - fpgaReadCmdBuffer[ 4 ] = 0; + fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize ); + fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize ); #else fpgaReadCmdBuffer[ 3 ] = jobSize; #endif @@ -933,7 +949,7 @@ } } - requestFlashRegistersStatus(); + //requestFlashRegistersStatus(); // TODO remove return state; } @@ -979,8 +995,8 @@ fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); #if BL_STACK_ID == 1 - fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; - fpgaWriteCmdBuffer[ 4 ] = 0; + fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); + fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); #else fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; #endif @@ -1047,7 +1063,7 @@ memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } - requestFlashRegistersStatus(); + //requestFlashRegistersStatus(); return state; } @@ -1115,7 +1131,8 @@ { if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) { - U32 rspSize = FPGA_READ_RSP_HDR_LEN + JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U16 jobSize = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; + U32 rspSize = FPGA_READ_RSP_HDR_LEN + jobSize; U32 crcPos = rspSize; U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); @@ -1125,27 +1142,33 @@ switch( fpgaJobsQStatus.fpgaCurrentJob ) { case FPGA_READ_HEADER: - memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) ); + memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], jobSize ); break; case FPGA_READ_UPDATE_REG: fpgaUpdateRegisterStatus = fpgaReadResponseBuffer[ FPGA_UPDATE_REQUEST_INDEX ]; break; + case FPGA_READ_MULTI_BOOT_STATUS: + memcpy( &fpgaReadRegsStatus, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], jobSize ); + break; + default: // Do nothing break; } memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); state = FPGA_IDLE_STATE; } } } if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) ) { + // TODO a request multiboot here state = FPGA_IDLE_STATE; } Index: firmware/BL.dil =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/BL.dil (.../BL.dil) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/BL.dil (.../BL.dil) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -1,4 +1,4 @@ -# RM46L852PGE 03/05/26 15:51:39 +# RM46L852PGE 03/14/26 14:33:06 # ARCH=RM46L852PGE # @@ -3852,7 +3852,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 @@ -4503,15 +4503,15 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000080 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=0x603 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 Index: firmware/include/can.h =================================================================== diff -u -r292265111b911fa79c52bb4589911dfb60c921bf -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/include/can.h (.../can.h) (revision 292265111b911fa79c52bb4589911dfb60c921bf) +++ firmware/include/can.h (.../can.h) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -647,6 +647,7 @@ | (uint32)0x00000010U \ | (uint32)0x00000020U \ | (uint32)0x00000040U \ + | (uint32)0x00000080U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ @@ -670,7 +671,6 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U) #define CAN1_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \ Index: firmware/source/can.c =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rab214e8ea52d8433b7cee58f5aaff49fc759310d --- firmware/source/can.c (.../can.c) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/source/can.c (.../can.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) @@ -120,6 +120,7 @@ | (uint32)0x00000010U | (uint32)0x00000020U | (uint32)0x00000040U + | (uint32)0x00000080U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U @@ -143,7 +144,6 @@ | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U - | (uint32)0x00000000U | (uint32)0x00000000U; canREG1->INTMUXx[1U] = (uint32)0x00000000U @@ -297,6 +297,25 @@ canREG1->IF2CMD = (uint8) 0xF8U; canREG1->IF2NO = 6U; + /** - Initialize message 7 + * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF1 control byte + * - Set IF1 message number + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x607U & (uint32)0x000007FFU) << (uint32)18U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 7U; + /** - Setup IF1 for data transmission * - Wait until IF1 is ready for use * - Set IF1 control byte